Cadence Custom Layout for beginners -RF IC design
Cadence Custom Layout for beginners -RF IC design It's the first time that I am creating a layout for an LNA design at 35Ghz. What should I read or watch for understanding how to create the layout,...
View ArticleRE: Connecting component body to ground on smd board
Hi. I think there are a few things going on here. The first is your actual footprint .Dra. In the data sheet for the package they have 5 pads and then one large grounding pad. This means that your...
View ArticleleHiCreateVia
Hi, I am facing an issue while placing via in layout. when I press 'o' in layout window it will execute ' leHiCreateVia' function and gives me an option to create via. If I create via this way by...
View ArticleRE: Converting Waveform data to list or vector using ocean Script
I tried this but it is giving me single value where my output is crossing 0.6 for the very first time, not for all time but for my work, i want the value for every time when it crosses the 0.6. I would...
View ArticleAdding Multiple values to single field in CIS database
Hi, I'm Using excel as my part database. I have to add two manufacturer part numbers in a single field named "MFGP/N". So When I try to place the symbol, I can choose which part number need to give...
View ArticleRE: Converting Waveform data to list or vector using ocean Script
One thing you could do is: foreach(crossPoint cross(v("/OUT" ?result "tran") 0.6 0 "either") printf("Crossing is %g\n" crossPoint) ; do you operation here ) The cross function, if given 0 as the...
View ArticleRE: Converting Waveform data to list or vector using ocean Script
Thank you SIr. It works.
View ArticleRE: unable to simulate this veriloga code in cadence
First you should read the Forum Guidelines . You didn't say where you were getting these parser errors (which tools, which versions) or what the errors are. I tried reading the file in spectre. There...
View ArticleVerilog-A import variables from file
I do have a lot (really a lot) of different variables in my Verilog-a model, like real var_00=0001; real var_01=0002; ... real var_FF=0003; As the huge number of variables make my code unreadable and...
View ArticleRE: Syntax for device checks associated to just one type of simulation
Andrew, That's fine by me. It was just the fact that the assert remains in the Violations display list even thought it's not applied. No problem with that. The designers will only look for FAILED...
View Articledynamic parameter in SpectreMDL
Hi, Basis: there is a need for me to change the temperature within the transient simulation. I followed the post as linked below, and got it working in Spectre from ADE...
View ArticleRE: leHiCreateVia
Hi Kumar, you should not use the "i" ( Create instance ) for creating vias, please always use the "o" ( Create Via) command. I don't know your PDK or the information you are referring to, but the vias...
View ArticleRE: dynamic parameter in SpectreMDL
Hi Everyone, It was my mistake, I missed the fact, "run tran" from spectremdl control file replace the tran from the netlist file. but I am still looking for any way to implement dynamic parameter...
View ArticleRE: Verilog-A import variables from file
Wouldn't the simplest thing be to create a file with all the real var_NN=val; lines in, and then include it into your model using `include ? Otherwise you're still going to need to declare all the...
View ArticleRE: Montecarlo simulation with Verilog-A and Python
Dear Andrew, Thank you for the explanation. I have read the ADE XL manual and found our that I can define model files as parameters as well. So, I think another work around would be to implement a...
View ArticleRE: Montecarlo simulation with Verilog-A and Python
I doubt it. It's going to be a lot of work (and is horribly complicated) and it's not obvious what benefit running Monte Carlo gives over a normal sweep. I'd certainly not do it that way and I'm pretty...
View ArticleRE: Verilog-A import variables from file
I first had tested this by running spectre standalone. I've now done it more like you suggested - as follows: Assuming I'm creating mylib/myblock/veriloga Create mylib/myblock/verilogaInc as a "text"...
View ArticleRE: eye diagram problem
Not really enough information - how are you running the simulation? Is the eye diagram added as an output in ADE L/XL (if so which) or are you generating it once and then updating it somehow? If so...
View ArticleRE: Adding Multiple values to single field in CIS database
The Manufacturer Part Number is reserved for the obsolete ICA fields, you probably need to have a table field named MFGP/N, or something like that, for this to work. No spaces between the alternatives...
View ArticleRE: How to put via in the center of BGA pins
It doesn't look like dimensions "a" and "b" are the same. A BGA fanout would be expecting a regular X / Y matrix and being able to use a 45 degree "dogbone".
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