RE: Verilog-A import variables from file

I first had tested this by running spectre standalone. I've now done it more like you suggested - as follows: Assuming I'm creating mylib/myblock/veriloga Create mylib/myblock/verilogaInc as a "text" view (not as a VerilogA view). In this text view create your variable definitions Then in mylib/myblock/veriloga you can add: `include "../verilogaInc/text.txt" That works with both the checker in Virtuoso - it finds the included file, plus when you run simulation. Regards, Andrew.