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RE: unable to simulate this veriloga code in cadence

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First you should read the Forum Guidelines . You didn't say where you were getting these parser errors (which tools, which versions) or what the errors are. I tried reading the file in spectre. There are two issues: The file has strange line endings. Normally on Windows you'd have "CRLF" (carriage return+line feed) or on Linux you'd have "LF" (line feed only). This has Carriage return only - and that seems to trouble the spectre parser (it troubles lots of things to be honest). I fixed that by doing (in Linux): mv ucsb_2dfet.va ucsb_2dfet_orig.va cat ucsb_2dfet_orig.va | tr '\r' '\n' > ucsb_2dfet.va Then it fails with this: Error found by spectre during AHDL read-in. ERROR (VACOMP-2259): "modulel<<--? tmdfet(S,D,Gt,Gb); " "ucsb_2dfet.va", line 5: syntax error. ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL compilation.... That's because at the beginning it starts with "modulel" and it should be "module". If I fix that, all is OK (well, it compiles and simulates - I can't vouch for whether the model works OK or not). Regards, Andrew.

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