Verilog-A import variables from file

I do have a lot (really a lot) of different variables in my Verilog-a model, like real var_00=0001; real var_01=0002; ... real var_FF=0003; As the huge number of variables make my code unreadable and confusing, I want to import these variables from an file. How can I do that ? What format is required for the file ? I want to use these variables as simple local variables in my code.