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RE: MonteCarlo simulation is taking much longer time than expected
I don't think I can answer these questions because it completely depends on how the sections in the model files have been written. It might be that they have statistical mismatch parameters in all...
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Padring Routing
Dear All, I am currently working with back-end design of chip an getting some problems. I've added a pad-ring by modifying my synthesized netlist and I've used PVDD1DGZ/PVSS1DGZ and PVDD2DGZ/PVSS2DGZ...
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RE: Where to find Allegro 17.2 new skill syntax/commands?
You can use the html or find the pdf on the support site. Apparently Cadence is trying to reduce the size of the delivery install files. I too would prefer to see the pdf files in the install folders.
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Spectre with a Red Hat, part 2
This is the second post about Red Hat's John Masters presentation at FOSDEM 2018 presentation Exploiting Modern Microarchitectures: Meltdown, Spectre, and Other Attacks . The first part appeared in...
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RE: Where to find Allegro 17.2 new skill syntax/commands?
You can look in \.config\cadence\PDFCache for the pdf files.
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3D Canvas Flex Bends
Hi, I watched this video so I know it is possible to bend areas of the PCB in the 3D canvas viewer. https://www.youtube.com/watch?v=trmPd_7_8yQ When I right click on the canvas or flex area there is...
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RE: Connecting component body to ground on smd board
Ah yes, I have used that part. You have a couple of options and depending on the current draw of the circuit the regulator may heat up too. If room permits you can place the part and connect it to a...
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Color of "tool tip" text
Hi, I seem to have inadvertently changed the color of the text of the "tool tip" (the bubble that shows up when you hover your mouse over a button in the GUI, for example when you hover your mouse over...
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RE: Illegal Character and Duplicate Pin Name
Thank you very much steve. i really appreciate your help.
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Converting Waveform data to list or vector using ocean Script
Hello, I am using "cross function" on the output waveform in cadence which is giving me a 2D vector( Multiple rows and 2 columns). wave=cross(v("/OUT" ?result "tran") 0.6 1 "either" t "time" ) I want...
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FILL* on schematic unbound LVS error
I have imported my .cdl netlist file which contains all the standard cell connection information along with FILL and ENDCAP cells. Normally due to unbound error, I have to run LVS with...
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Syntax for device checks associated to just one type of simulation
Hello, I am creating a number of device checks in ADE using a separate file (devcheck.scs let's say). I wondered if there was a way to specify that a check just be performed against one type of...
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RE: 3D Canvas Flex Bends
You need to Anchor the 3D View before you can apply bends. Setup>Anchor 3D View, pick a point for the anchor, in the middle of the left hand Zone for example, and the Bend will be enabled in the 3D...
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RE: MonteCarlo simulation is taking much longer time than expected
Dear Andrew, Thanks a lot. I will talk to the foundry people for the exact clarification. Kind Regards,
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RE: Component RefDes / page number problem - Allegro Design Entry HDL...
I think that the key is that you have to do a "Save Hierarchy" before you package. What that does is it will basically re-save the instances of the components you copied to that specific page. Nothing...
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Automate creation of pins in a top level layout directly above sub-cell pins
I am utilizing a 3rd party EM simulator that can automate the creation of ports by utilizing top-level layout pins. My layout makes use of PDK PCells that have their own pins. I'd like to create new...
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App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right...
Welcome to another App Note Spotlight! One of the biggest issues facing verification engineers is the question of reducing elaboration time. Using incremental elaboration (MSIE) can greatly reduce that...
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Whiteboard Wednesdays - Error Correction Code Implementations in Memory...
In this week's Whiteboard Wednesdays video, Jing Liu provides a simple explanation of the in-line and out-of-band methods of Error Correction Code (ECC) implementation in memory subsystem designs....
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unable to simulate this veriloga code in cadence
To the respected form members I am noob to this I have a Veriloga code with me but I am facing parsing error with it The code is genuine and i want to know where it get wrong thank you. code:...
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