Dear All, I am currently working with back-end design of chip an getting some problems. I've added a pad-ring by modifying my synthesized netlist and I've used PVDD1DGZ/PVSS1DGZ and PVDD2DGZ/PVSS2DGZ as core and I/O power pads and I am using libraries. In the Encounter, when I use sroute to route the padring , I am getting the following warning: **WARN: (ENCSR-1255): Cannot find any non'CLASS CORE' pad pin of net VDD. Use 'CLASS CORE' pad pins of net VDD to create padring. **WARN: (ENCSR-1255): Cannot find any non'CLASS CORE' pad pin of net VSS. Use 'CLASS CORE' pad pins of net VSS to create padring. I am new in the chip back-end design and would like to know more about routing of pad-ring and I/O power pads. Do we supply external separate power supplies for core power pads and I/O power pads, or there is some internal power conversion and how do we route them? Thanks, Saleh![]()
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