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RE: How to quickly find device category?
Hi Andrew, I am new to the community.cadence.com, many thanks to you as your solutions for different users queries are helped me a lot. Please help me to get solution for below query, Can we get list...
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Visa, Priceless
Well, okay. It's actually Mastercard that runs those "priceless" ads, not Visa. But this post is about visas, mostly the H-1B visa, since we don't have too many H-2A temporary agricultural workers in...
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COMPONENT FLEXIBILTY IN PART EDITOR OF ORCAD CAPTURE
HIII Guys...I hv a small query regarding orcad capture symbol editor..As i create any SYMBOL the pins are not moving smoothly though i uncheck the SNAP TO GRID option in the settings..I disbale the...
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RE: COMPONENT FLEXIBILTY IN PART EDITOR OF ORCAD CAPTURE
Why would they? The theory is: Pins are on the grid in the Part, the Part is placed on the grid in the schematic and, therefore, wiring to the pins does not involve any challenge requiring "exact"...
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What's Exciting About Being An Application Engineer? Watch This Video!
Many of you may not be familiar with what a Field Application Engineer (most often shortened to FAE or AE) does. AEs at Cadence are critical in making our customers successful by helping them with not...
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RE: straight line (best) fit using viva calculator
Hello Andrew I use positively this function and it is great ! Thank you very much !
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PADS Translator of PCB and Library loose all the swappability info
I have done some test and seems that Pad Translator loose any swappability info of the components. It generate always 1 gate containing all the pins. Also all the pins are NOT swappable. the sama...
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PADS Translator of PCB and Library loose all the swappability info
I have done some test and seems that Pad Translator loose any swappability info of the components. It generate always 1 gate containing all the pins. Also all the pins are NOT swappable. the same...
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RE: Can't generate netlist in orcad capture CIS
Problem solved! I was dumb >< and thank you redwire :3
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Verilog-A to access wire bus of DUT
I am trying to create a verilog-A model to extract bus of nets of my DUT in a similar manner to the component deepprobe from analogLib in a Spectre transient simulation. These buses are at least 20-bit...
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Page Order in Hierarchical Design DE-CIS 17.2
Is there an automated method (not manual) for controlling the page ordering in a schematic design with a complex hierarchy? Manual editing will only cause problems as pages are added and deleted. For...
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ModGen and Common Centroid Layout
Hello, I am trying to use ModGen to do Common Centroid Layout in CMOS using ModGen and Contraint Manager. Is there a tutorial/RAK about this ? I am getting some errors and wondering if they are kit...
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get list of cells under specified Category which has recursive subcategories.
Hi, I am new to the community.cadence.com, Please help me to get solution for below query, Can we get list of cells under specified Category - MOSFETS (which has again a subcategory branches, like...
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irun is not recognizing .scs files
I am running ams irun simulator Cadence IC6.1.6-64b.500.2 I get the following error: irun: *E,FMUK: The type of the file (./spiceModels.scs) could not be determined. irun: *E,FMUK: The type of the file...
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RE: irun is not recognizing .scs files
Hi Eric, It looks to me that you are using a very very old incisive version where irun does not support .scs file. You can find the irun version you are using either at the top of the irun.log or if...
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RE: Editing Signal names in ViVA
Hi Dimitra, I have old version, so tried with command given here. Its working well. Thank you so much Regards, Vijay
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Installing cadence 16.3 in windows 10,64 bit
while installing cadence 16.3 in windows 10,64 bit.The dongle is not installing.Please help me tosolve this issue...... Does cadence does not support windows 10?????
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RE: ModGen and Common Centroid Layout
Hi, Not sure how you do Common Centroid on your Modgen. You can use the "Common Centroid" Pattern Preset which is available in the Grid Pattern Editor Assistant in the Modgen Editor. There is this RAK...
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Changing x-value of a signal and/or handle signals with multiple outputs
Hello, My question from https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38589/image-rejection-of-iq-mixer is still up :( So far I found the following hack: PSS+PAC, relative...
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RE: Verilog-A to access wire bus of DUT
Hi, I don't think that the extract fails because of the bus syntax. I think the failure happens because OOMR nodes can only be constant or parameterized. From the Verilog-A Language reference, it looks...
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