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OrCAD Trial Versus OrCAD Lite: Try Full Power or Carry on with the Limits?
Sarah is a sophomore at a reputed university pursuing her undergrad in engineering. She knows OrCAD® Capture and PSpice are part of ECE-240. But when she wants to download the software, she has an...
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Metal routing not getting extracted
Hi! Some of the metal routings are not getting extracted during QRC extraction. I have a screenshot of av_extracted view to explain my problem. As can be seen in the image, some part of metal is not...
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RE: Metal routing not getting extracted
Hi Praveen, Can you share your QRC command-file as well? The Metal1 shapes that are extracted and not extracetd - are they at the same level of hierarchy in the layout? I noticed you are looking at...
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RE: Metal routing not getting extracted
This is the command file (also added in answer). The shapes that are getting and not getting extracted are in the same heirarchy. I am sorry, but I did not understand the last point. In the extracted...
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[URI] RelXpert support for HISIM_HV model cards.
Hello All, I am implementating an aging model using the URI for a transistor techonology using a HISIM_HV model card. The implementation works fine when I run the simulation using the Spectre Native...
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RE: Metal routing not getting extracted
Hi Praveen, Okay I just noticed that you are already displaying all used layers, and everything in extracted view is in pin layer. Even if you don't see the shape divided into rectangles, its...
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A New Era Needs a New Architecture: The Tensilica Vision Q6 DSP
There is a trend for increasing sophistication in vision and in artificial intelligence (AI). There are many drivers of this, but two of the most important are the advanced capabilities of high-end...
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Whiteboard Wednesdays - New Tensilica Vision Q6 DSP for Vision and AI Processing
In this week’s Whiteboard Wednesdays video, Pulin Desai, discusses the features and benefits of the fifth-generation Tensilica Vision Q6 DSP used for vision and AI processing. www.youtube.com/watch
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Can't generate netlist in orcad capture CIS
Hi everyone I'm looking for a format/standard/help document that how to form a netlist fie can be imported to orcad pcb editor for a developing program I wanted to get a sample from my circuit, but...
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RE: searching a list of sublists for matching expression
great examples both - thank you! rexMatchList was handy. I only have one level of hierarchy, but the recursive search example is much appreciated.
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addStripe command for multiple power domains
Hello, I have multiple (6) power domains in my design. I am placing stripes using the addStripe command but every time I am ending up with a design in which the rails are extending outside the selected...
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RE: Can't generate netlist in orcad capture CIS
You need to make sure you are at the top of the project folder. If you are on a schematic page view you can not generate the schematic... Can you post a screen shot of the trouble?
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Image Rejection of IQ mixer
What is the easiest way to simulate image rejection of an I/Q downconversion mixer - if possible with pss/pac? Suppose the mixer is a black box with a PORT at the LO input (which generates 0 and 90...
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RE: via connection quandary
Hi John, Here is a picture, verify you have enough clearance between your shape and vias ! Regards Paul.
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RE: Metal routing not getting extracted
Hey! I used the fracture length of 5 squares to show the difference between extracted and non-extracted part. Initially, I was using infinite microns fracture length but then I wouldn't be able to show...
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RE: Verilog A ADC design
Thanks, Sir. That solved the problem. Can you say how did you create the 10-bit bus for the 10-bit output? I am facing some difficulty in doing that.
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RE: Metal routing not getting extracted
Hi Praveen, It will be difficult to debug this issue further without looking at the data, so I suggest you contact customer support. Regards, Saloni
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Make synchronous copy(not clone) from cadence SKILL
I have a code which auto stacks Source/Drain of the FET transistors. Lets say i have made this procedure named "STAK". Lets suppose i run this procedure STAK to run over a FET having 5 Sources and 5...
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Error detected in psf library while writing to file `tran.tran'.
Hi, I am using virtuoso to simulate my 30k gates design and in the process i am saving all the signals along with power signals. After 2.5ms (2.27 %) of the simulation, i am getting a fatal error "...
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RE: Error detected in psf library while writing to file `tran.tran'.
Hi, This error typically indicates insufficient diskspace but you mentioned that this shouldn't be an issue. Can you share your simulation log (spectre.out)? Regards, Saloni
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