This is the command file (also added in answer). The shapes that are getting and not getting extracted are in the same heirarchy. I am sorry, but I did not understand the last point. In the extracted view I just have pins for every layer in the palette. I didn't understand how to check what I see in Metal1 net (or drw - drawing?) https://drive.google.com/file/d/1g_yEiW0dg6qJb6pssnVpHlYfNkOKcQkj/view?usp=sharing #-------------------------------------------------------------------------------------- # OPTION COMMAND FILE created by Cadence Extraction Quantus QRC UI Version 15.22-s247 #-------------------------------------------------------------------------------------- capacitance \ -decoupling_factor 1.0 \ -ground_net "/gnd!" extract \ -selection "all" \ -type "rc_coupled" extraction_setup \ -array_vias_spacing auto \ -max_fracture_length 5 \ -max_fracture_length_unit "SQUARES" \ -macro_cells_type "default" \ -max_via_array_size "auto" \ -net_name_space "SCHEMATIC" filter_cap \ -exclude_self_cap true filter_coupling_cap \ -coupling_cap_threshold_absolute 0.01 \ -coupling_cap_threshold_relative 0.001 filter_res \ -merge_parallel_res true \ -min_res 0.001 input_db -type assura \ -design_cell_name "cc_r3sw_metres_3 layout sgb25_schem_lay" \ -run_name "lvsrec" \ -directory_name "/data/ee15s015/userP/cds/LVS" \ -format "DFII" output_db -type extracted_view \ -cap_component "pcapacitor ivpcell SGB25_dev" \ -cap_property_name "c" \ -enable_cellview_check true \ -include_cap_model "false" \ -include_parasitic_cap_model "false" \ -include_res_model "false" \ -include_parasitic_res_model "false" \ -res_component "presistor ivpcell SGB25_dev" \ -res_property_name "r" \ -view_name "av_extractedrc5" output_setup \ -temporary_directory_name "lvsrec" process_technology \ -technology_corner \ "default" \ -technology_library_file "/data/ee15s015/userP/cds/assura_tech.lib" \ -technology_name "SGB25_dev" \ -temperature \ 27![]()
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