RE: Verilog-A to access wire bus of DUT

Hi, I don't think that the extract fails because of the bus syntax. I think the failure happens because OOMR nodes can only be constant or parameterized. From the Verilog-A Language reference, it looks like you can not use string variable. Cadence Verilog-A Language Reference -- 9 - Out-Of-Module Reference So you will need to replace ' string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK "; ' with ' parameter string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK "; ' - you can also use localparam. Or you can use the literal string directly in the branch contribution statement, ' V(NetOfInterest01) "); '. Regards, Dimitra