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CDNLive Keynotes: What will Drive the Future?
The new season of CDNLive kicked off earlier this week with CDNLive Silicon Valley in the Santa Clara Convention Center. The giveaway this year for visiting enough of our partners in the expo was the...
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(Cadence Genus Synthesis) How to use more than one library file for synthesis?
Below is my Genus synthesis script.tcl, #Script #Setting Library and Design Path set_attribute lib_search_path ../lib/ set_attribute hdl_search_path ../design_files/ #Setting Library and Design Files...
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Hierarchical Design using characterized blocks timing issues
Hello, I am trying to build a hierarchical design using Innovus, but I have a problem with closing the timing. My design is composed by different clone and master blocks. I partition the design and I...
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IMC Coverage figures in ascii report differs from GUI & html report
Hi all, I have problems to get the same coverage figures shown in the GUI & html report versus the plain ascii report for a toplevel module. I am using the following script: merge -overwrite...
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RE: get list of cells under specified Category which has recursive...
Hi Basavaraj, Can you please share your code and explain a bit more your example? I don't understand how your subcategories are structured by saying recursive subcategories. You cannot have a...
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RE: irun is not recognizing .scs files
Thank you. This was extremely helpful. It turns out that there was an old INCISIVE version buried in the directory structure, and it was included in my $PATH. Fixing the path to only include the new...
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How can you move/stretch schematic wires WITHOUT Virtuoso rerouting...
I did try searching for this answer, but got lost in the zillions of search results so I thought I'd try here... I have a schematic that I've carefully and neatly laid out. If I edit it to do things...
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RE: How can you move/stretch schematic wires WITHOUT Virtuoso rerouting...
Groan - after looking around for this answer for quite a while, it just now fell into my lap. It's an embarrassingly obvious answer, so let me beat everybody to it and be the first one to call myself a...
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RE: Importing PADS footprint into Allegro 17.2
Is there a way to do this without PADS? Like say if I only have Allegro?
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How Allegro is calculating Via delay (Z-axis delay) from propagation velocity...
Hello Group, I really had a hard time to identify formula through which Allegro is calculating via delay (z-axis delay) from propagation velocity factor. In CM, default value for propagation velocity...
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RE: Importing PADS footprint into Allegro 17.2
Hi dgrolnu, you need to extract the *.p and *.d files from pads. Is not possible in Allegro (also OrCAD PCB) to extract them from original pads libraries *.ld9, *.ln9, *.pd9, *.pt9 files. At the moment...
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RE: Importing PADS footprint into Allegro 17.2
i have noted another error. the translator routine use for the internal pads definition for all internal layers NOT the definition of the internal pad of PADS, but the diameter of the antipad pad of...
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Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases, but strangely i can see the possibility to see my cases already...
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Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases, but strangely i can see the possibility to see my cases already...
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RE: Possibility to open Cases and how to ask improvements on PCB designer
Submitting a new case: Go to support.cadence.com, in the top menu bar, hover over "Cases" and select "Submit Case" If those options are not available, then my guess is that your host ID entered is not...
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Dangling wires/extra net length using -sroute command
Hello, I am using multiple power domains in my design and while doing the routing of power structures (using the -sroute command), I see that the VDD_CORE1 wire (in my case) always extends by a small...
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File Type Clarity - Using Built-in Capture Symbol Models to Create...
What I'm trying to do... I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I change...
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RE: File Type Clarity - Using Built-in Capture Symbol Models to Create...
Also I'd like to use the 4 terminal device as well, and this seems to be maybe unavailable to make your own custom variant?
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RE: PSS not completing in post extraction design
Hi! I realized that PSS uses RAM to store data. When I ran the analysis on a machine with 256 GB RAM the analysis completed. However, it used up 242 GB of memory and thus there is no memory left for...
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IC617 import GDS file from TSMC.
Hi, Can I ask a favor? I am trying to import an io pad lib from TSMC into Cadence IC 617. This is how I tried to do it. I firstly create a library , name it io_pad and attach it to my TSMC PDK library...
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