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RE: Can ViVa display internal variables of VerilogA model?
Hi David, This works for me. What subversion of Virtuoso are you using? Regards, Andrew.
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RE: Converting Waveform to list
Hi Savino, That's not unreasonable. I don't really know what you're doing with the results of abWaveToList, so whether there's a better way, I can't comment. Regards, Andrew.
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Achronix Grew 700% Last Year...eFPGA is a Thing
I don't normally write about the FPGA market. There are three reasons for this. First, Cadence doesn't participate in the market for FPGA tools (for FPGA users. I'm pretty sure the arrays themselves...
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RE: removing repetitions from list with same elements but in reverse order
Hi Andrew, Thank you so much Andrew.This is what i exactly wanted. Regards, Raghu
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Virtuosity: What's New in Run Plan – Part II
I wrote about new enhancements in Virtuoso® ADE Assembler Run Plan feature in Part I . This blog is continuing on the same topic concentrating on additional enhancements added since IC6.1.7 ISR15. How...
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layout XL extract cellviews in hierarchy?
In Virtuoso Layout XL->Extract layout, what is the function of the Scope setting "Current Cellview and Cellviews in Hierarchy", and of the "Save Extracted Cellviews" button? Does that Scope setting...
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RE: How to plot frequency characteristic of capacitance?
Hi Kawai, It sounds as if you're just not looking at the results properly - did you do what it suggests in the error and see what results() returns? This is something that would be best handled with a...
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memory leak?
Are there any known ways to confuse the garbage collector in skill? I have a moderately large simulation that uses Ocean to step through a number of conditions. For each condition, there is a transient...
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RE: Can ViVa display internal variables of VerilogA model?
hi Andrew, good to know it's possible. Just figured it our when I tried to explain why it didn't work my side. I just have to save more . thanks, David
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possible to instantiate Verilog module in VerilogA?
Hello exports, wonder is it possible to instantiate Verilog base sub-block in VerilogA? I just did the following instantiation code but how can I tell the simulator where the Verilog code is? test test...
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RE: possible to instantiate Verilog module in VerilogA?
Hi David, Only verilogA or spice blocks can be instantiated in a hierarchical verilogA module, so you cannot instantiate a verilog module. Regards, Saloni
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RE: possible to instantiate Verilog module in VerilogA?
thanks Saloni, looks like it. if I put in a VerilogA instance in, it'll see it in the hierarchy editor. it doesn't do the same thing if I instantiate a Verilog module (I do have connectLib available)....
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CGTN China 24 Interview
https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week, being interviewed about the Chinese Semiconductor Industry. www.breakfastbytes.com Sign up for Sunday Brunch, the weekly...
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how to convert text string to integer in VerilogA?
hello experts, in VerilogA, "reg" is not supported in Cadence yet even it's described in the Cadence version of VerilogA manual, and I'm having a hard time to pass some text string into integer value...
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RE: Greyed menu: "Run Assura Quantus QRC..." and "Run Assura Quantus QRC..."
I just solved this error of license setting ASSURA_USE_PVS_LICENSE ambient variable. But, it did not solve my problem. I cannot run Assura QRC, because its menu is grey. I just can run Setup Quantus...
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RE: possible to instantiate Verilog module in VerilogA?
David, You could put the VerilogA code in a VerilogAMS view, and then you should be able to instantiate Verilog (digital) within the block and simulate it in AMS. The issue is that VerilogA is an...
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RE: how to convert text string to integer in VerilogA?
Hi David, Which manual are you looking at? I just looked at the Cadence® Verilog®-A Language Reference manual from SPECTRE17.1 and there is no mentioned of "reg" there. I'd be surprised because it's a...
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I want to learn PCB design
I want to learn PCB design , is there anyone to give suggestions that how to start , and what need to learn about frist ? Best regards Thejigsaw
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RE: memory leak?
Hi Dan, Please contact customer support about this. I recently filed a CCR related to memory growth when certain waveform manipulation functions in OCEAN where memory growth was only partly abated by...
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RE: Greyed menu: "Run Assura Quantus QRC..." and "Run Assura Quantus QRC..."
The problem remains but I know now that it may be an installation problem. I just ran "qrcui" from " /EXT181/tools/extraction/bin/64bit" in a terminal. It appears the QRC menu in a single window. From...
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