Hi David, Which manual are you looking at? I just looked at the Cadence® Verilog®-A Language Reference manual from SPECTRE17.1 and there is no mentioned of "reg" there. I'd be surprised because it's a digital construct and so makes no sense in the analog Verilog-A language. If it was the Cadence® Verilog®-AMS Language Reference manual from an INCISIVE or XCELIUM stream (may be in the IC stream too - I forget) then that would make more sense, but then it would be talking about Verilog AMS and you'd have to use a Verilog AMS view and simulate it in AMS Designer. Regards, Andrew.![]()
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