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RE: File status (checkedout/checkedin/unmanaged)
Sure, here it is: Cadence Application Infrastructure User Guide -- 8 - gdmstatus Regards, Dimitra
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6 Ways to Get the Most Out of CDNLive
It's CDNLive! Well, not today, Tuesday and Wednesday this week at the Santa Clara Convention Center. So I have six things you can do to get the most out of CDNLive and go home with a cute cuddly bear....
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RE: PSS not completing in post extraction design
Hi, Can you set the 'Post-Layout Preset Mode' to 'Legacy-RF RCR' instead of 'Legacy RCR' ? This will print +postlayout=legacy_rf out in the spectre command in the spectre.out log file. The legacy_rf is...
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= and => conflict, did IEEE spec resolve that?
Hello, According to ieee.1364 9.2.1: “A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1)” and 9.2.2:...
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axlMapInstTermToNet() and DSPF view
Here is my Vituoso version: "@(#)$CDS: virtuoso version ICADV12.3-64b 11/21/2017 19:22 (sjfhw308) $" I am trying to save and plot the signal connected to the gate terminal to a transistor by using...
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Jumper & Single Side PCB's
Dear All I m an newbie to Orcad PCB Designing Suite & Application, I hope I m not repeating the stuff again, Earlier I worked on PCB's and PCB Designing through Ares, Due to user friendly nature it...
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`case' expression with list literal behaves differently in pcDefinePCell than...
;; The `case' expression in this pcell is expected to return "V2", but it ;; returns `nil' instead. Why? (pcDefinePCell (list (ddGetObj "dungeon") "case_in_pcell" "layout") ((metal1_layer "M2")...
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RE: `case' expression with list literal behaves differently in pcDefinePCell...
Hi Tom, I don't see the variable via_layer being assigned, but also I am a little confused by the format of your case statement, partly because I know that 'case' allows for alternative matches in the...
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RE: `case' expression with list literal behaves differently in pcDefinePCell...
Hi Lawrence, Thank you for fixing my bug! You're right, adding the setq fixed it. ^_^; Somehow this equivalent code (with the setq) does not work inside my org's custom pcell compiler, however.... But...
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pp output of `case' expression in procedure definition changes after the...
After further debugging, I believe I have gotten to the root cause of my `case' woes: > getVersion "@(#)$CDS: virtuoso version ICADV12.3-64b 09/01/2017 10:34 (sjfhw305) $" > sstatus printinfix...
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RE: How to continue execute a skill script after a form popup in layout ?
I did not know about hiEnqueueCmd, so I had been using hiRegTimer for driving blocking forms. If hiEnqueueCmd is what I should have been using, than what is hiRegTimer's raison d'être ?
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Monte Carlo Simulations of Extracted Layout
Hello, I wanted to do the Monte-Carlo simulations on a extracted layout (DC analysis). As recommended by a previous comment , I made a "config" view for the test-bench and did the DC analysis in ADEL...
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searching a list of sublists for matching expression
Is there a simple way to search a set of sublists for matching expressions and return the list of sublists that have the expression? I have been trying the following example and only get the full...
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RE: searching a list of sublists for matching expression
It looks like you were trying to do something like this: setof(list mylist destructuringBind((first second) list string(first) && rexMatchp("one" first) ) ) You could also write that this way:...
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Move ports in symbol created for module
This is something that has bugged me for a while and I have not yet found a solution: we often re-use schematics in the form of modules. Typically, we create the module following a procedure similar to...
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RE: How to read label inside a particular instance and check its connectivity...
Hi Garima, You may use dbGetOverlaps(..) to get at the shapes in the master cell that are overlapped by your metal routing, the below SKILL expression returns a list of those shapes: (foreach mapcar sl...
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RE: Move ports in symbol created for module
As a workaround, I have gave up with the idea of having ports named XXX_N. It seems that whenever a port is named like that, Allegro tries to do something clever. unfortunately, this cleverness results...
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RE: Monte Carlo Simulations of Extracted Layout
Hi, Does this error pop up in the beginning , middle or end of the postlayout simulation? Once you click on the "Close" button in the pop-up form, what errors you get in the Results tab? Select one of...
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RE: searching a list of sublists for matching expression
If you have no idea about the list structure (how many nesting levels etc...) I think you need to recursively walk through the list in question...try this one: (defun searchList (theList regex "lt")...
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