Hello, According to ieee.1364 9.2.1: “A blocking procedural assignment statement shall be executed before the execution of the statements that follow it in a sequential block (see 9.8.1)” and 9.2.2: “The nonblocking procedural assignment allows assignment scheduling without blocking the procedural flow.” The basic is that for blocking =, compiler calculate a dependency graph first, then simplify to combinational logic; for => it is simultaneous assignment. Just as ieee C++ spec doesn’t stipulate how virtual table is to laid out (as there are IA64 and MSVC ways to do that), the 1364 spec lacks further restrictions. 1) Conflict: if Reg A is being assigned in an always block in both categories a. First among blocking =’s, then among =>’s, how to resolve? b. First among =>’s, then =’s, how? I know that for a) case, Quartus basically accept that, but would prohibit any further blocking assignment. How does Cadence tools treat this? 2) There is a question that for 9.2.1 =’s, because it is defined to be sequential, it somehow suggest the existence of clocks, and indeed #n delay can be added for simulation, and in fact some document suggest that maybe a decade ago there were tools also adding clock delays for #n into synthesis, but that requires knowledge of the specific clock design. I could not find definitive clarification in IEEE standards on this. If, for some ill-define =’s statements, assignment for registers unavoidably require adding delay to ensure correctness , how does Cadence NC tools treat them? Does Cadence conform to any standards in doing that? Regardfs, G![]()
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