Here is my Vituoso version: "@(#)$CDS: virtuoso version ICADV12.3-64b 11/21/2017 19:22 (sjfhw308) $" I am trying to save and plot the signal connected to the gate terminal to a transistor by using axlMapInstTermToNet(). This function works well with the schematic. It also works well with the StarRC view. Since netlisting of the StarRC view takes really long time for larger designs, I use the extracted DSPF views instead. My problem now is that axlMapInstTermToNet() does not work with DSPF views. Here is my question: Are there any other skill functions or customised skill scripts to map the terminal name to a net name in the final netlist including the dspf view? What I am doing now is to dump the final netlist from the Spectre simulator by adding this nodesinfo info what=nodes where=file file="nodes.info" in the netlist and run a empty simulation to dump nodes.info. Now I can parse the nodes.info so that I can map any terminal to a net name including the DSPF views. However, this approach need me to dump this file first before I can do the map properly and the terminal names in nodes.info are different from the schematic terminal names, i.e, "g" vs "G" or "GATE," and I do not know how to map the schematic terminal names to Spectre terminal names. I checked asiMapTerminalName(), ciMapTerm(), ciMapTermName(), and hnlMapTermName() and still could not figure out how to do the terminal map properly. I feel that it has something to do with how the PDK names the terminals vs how Cadence schematic names the terminals and how the netlister translates and maps them. Thanks, TJ![]()
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