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Component parameter DC Sweep
I found the following thread trying to troubleshoot my problem: https://community.cadence.com/cadence_technology_forums/f/rf-design/21507/working-with-dc-sweeps-and-op I am trying to do the same thing...
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RE: Assura LVS- Where should I specify RSF
Hi nokta You can also refer to "Setting Up Technology Data' chapter in $ASSURAHOME/doc/assuradev/assuradev.pdf (Assura Developer's Guide) for more info on techRuleSets file. Best regards Quek
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RE: How to Find the location missing of assembly component subclass BY SKILL.
I thiink about it like this to resolve this request. ####################################################################### Method: - Choose layer check: ASS_TOP; ASS_BOT - Vissible Layer Active -...
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RE: Component parameter DC Sweep
Hi Kevin, Two things. First of all, the hierarchy separator in spectre needs to be "." not "/". The forward slash is what is used in Virtuoso, but not in spectre, which needs a dot. So it would be save...
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reading sens1 values from dcOpSens is very slow
Hi *, I'm trying to read some data from a dc sensitivity analysis. For now I have two nested foreach loops something like foreach(refSig refSigList foreach(instName instDataTable // some code sensVal =...
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how to hide "DO NOT INSTALL" components
"Do Not Install" components are crossed out in variant schematic, how can I hide them? Instead of seeing crossed out components, I want to hide these components instead.
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RE: reading sens1 values from dcOpSens is very slow
Hi Marcel, I'm not sure this will be any quicker, but I'd do it as follows: selectResult('dcOpSens) dataType=car(dataTypes()) ; probably just "sens1Req") foreach(output outputParams(dataType)...
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how to display refdes rats on manufacturing-assembly drawing
Hi, how can I display the refdes rats on the manufacturing-assembly drawing for variants?
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RE: reading sens1 values from dcOpSens is very slow
Hi Andrew, It is perfect for now: run-time decreased 3 times. I have to run it on a bigger testcase. Best Regards, Marcel
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APS/Spectre simulation data too big
Hi All, I remember we have an option to select less data point to reduce the simulation file size? For example, the real simulation runs 10 point, but we can configure it to save only one point from...
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RE: APS/Spectre simulation data too big
Hi Andrew, Several ways to achieve this. One is to use the transient option skipcount which does exactly what you want (skipcount=10). Another approach would be to use strobeperiod which asks the...
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RE: RC compiler and ports consisting of arrays of vectors
Hello Olivier, not really, I did some work around like building a wrapper so I was able to reuse the original test case setup. Depending on the array size this can be an ugly job... Best regards, Markus
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Custom digital placer can't use tap-cell
I have declared the tap-cell as STDSUBCONT in CPH, however custom digital placer aborts any attempt to use it with *WARNING* (VCP-20003): No tap cell masters could be found. Define tap cells and...
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TCL Script for adding wires on SoC Encounter
I'm using SoC Encounter for my ASIC implementation, I route some nets manually by adding wires in the GUI (shift + A). I want to do that by some commands in my tcl script. Supposedly when doing...
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RE: Component parameter DC Sweep
It was the first part that was tripping me up, changing the "/" to a "." solved the issue. That's great that saving operating point parameters is now built into ADE, it will make my life much easier!...
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RE: Generating Layout - pcellEvalFailed
As you said, I checked the CIW and I found a problem about "libInit.il" file. After I fixed it now it works well. Thank you
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RE: layout object purpose number directly?
Thanks. I figured out a solution which I'm adding in case others find this thread in a search (or I find it in a few years). 1) As Andrew mentioned, "techGetPurposeNum" is what should have been in the...
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Vector files and verilog ams modules
I have made a verilogams module for a 2 to 4 decoder where both the input and output buses are logic disciplines. I then made a test bench for the module which consisted of a verilog a model of a...
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RE: Vector files and verilog ams modules
sorry mods can move this post to the Mixed Signal design forum. thanks
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RE: how to hide "DO NOT INSTALL" components
You can set "Part not Present" color to match the background when you view the schematic in variant view mode.
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