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Sigrity Power DC - DCR value for inductors
Hi Folks, I'm new to sigrity power dc tool. Inductor has DCR 42 mOhm and current flowing through the PDN is 2.2 Amps. So the voltage drop across the inductor is 92.4mV. It is very high IR drop in my...
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How to setup and simulate differential TDR
Hi, I want to do differential TDR simulation in cadence virtuoso. I have a differential channel, made of Tlines and interconnects (passive componenets). How to setup the TDR simulation to get impedance...
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RE: Installation of EXT151 from hotfix file
Thanks for your support. We installed hotfix file with installspace. It works. Sincerely
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Assura LVS- Where should I specify RSF
Hello, I imported a new library, umc130nm. I also defined it in assure_tech.lib file. While I try to do LVS, I choose these technology. But after I click to Apply/OK, I see this error: Neirther...
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How to check missing assembly BY SKILL.
Some issues design appear when I completed and check overall before releasing my design. And I need to check on ASSEMBLY which it is missed by created manual of designer. Dear Mr Dave and all members...
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How to Find the location missing of assembly component subclass BY SKILL.
Hi, Some issues design appear when I completed and check overall before releasing my design. And I need to check on ASSEMBLY which it is missed by created manual of designer. Dear Mr Dave and all...
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The First Sushi I Ever Ate Was in Japan
In the first installment, I wrote about why I had to visit Japan in 1983, and the semiconductor stuff I did there. Today, it's all the other stuff. Japanese Food When I went on this first trip to...
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RE: Assura LVS- Where should I specify RSF
Hi nokta The usual Assura setup is as follows: a. Create an "assura_tech.lib" file in the working directory where you start Virtuoso b. The file should contain a line similar to this: define umc130nm...
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RE: PVS LVS reporting missing pins in Layout
Hi Waleed Perhaps you can try this: a. Execute the following cmd in a terminal window: terminal> egrep "port -text_layer" /your-path/PVS_LVS.rul You may get something similar to this: port...
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RE: how to change display option of a cell initially ?
Obviously you wouldn't want all parameters to be displayed by default - it would be too cluttered for all devices. So I don't think that makes sense. This cyclic field is not the CDF way of displaying...
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RE: Assura LVS- Where should I specify RSF
Thank you Quek, it worked. But would you tell me, is there any way to learn this expect that asking here. In my library, there was no tectRuleSets file btw. I added it.
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RE: What do the checkmarks in RMB menus mean?
I've noticed this too; the checkmarks appear to have literally no effect, just a display artifact, aka, another bug by Cadence.
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Generating Layout - pcellEvalFailed
Hello, After I created my schematic with umc130nm library, I tried to draw layout with Layout XL. When I try to generate all from source ( left bottom button) it put component but after I push "...
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RE: Issue: Updating footprints and padstacks in Allegro 17.2
Hi, I will give you a quick crash course on how to embedded a component. 1. Open the Cross Section Editor and change the Embedded Status to "Body Up" for the layer you want the component placed 2....
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RE: Generating Layout - pcellEvalFailed
This will either be due to a bug in the PDK, or something wrong with your setup of the PDK. When the pcellEvalFailed appears, there's probably a warning in the CIW telling you more detail. Or you can...
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RE: Generating Layout - pcellEvalFailed
After I use Verify->Marker->Explain and click to error, it says "(GE-1013): The highlighted marker belongs to cellview umc13nm/N_12_HSL130E/layout and its reason is: ("eval" 0 t nil ("*Error*...
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RE: Generating Layout - pcellEvalFailed
No - I can't find anyone else who has reported an error due to this function being missing (it's not a Cadence-provided function). I suspect it's because some code isn't being loaded - I'd suggest you...
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Unable to import psm path
Problem Statement: I am not able to re-import all of my libraries I used in the 16.6 in the 17.2. I pointed to the original files and they didn't import then I pulled all the pad, psm, and dra files to...
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RE: Issue: Updating footprints and padstacks in Allegro 17.2
Thanks Mike! I was unaware of this feature, but it worked out great! The only problem is that one of the pads in my footprint has a plated via array embedded in the padstack that connects to a pad on...
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RE: How to Find the location missing of assembly component subclass BY SKILL.
I'm not sure what you are asking. You say ASSEMBLY is missing. Do you mean the assembly outline of a component, a reference designator, a layer from a mask or something else? Extracts can be big. I...
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