Vector files and verilog ams modules

I have made a verilogams module for a 2 to 4 decoder where both the input and output buses are logic disciplines. I then made a test bench for the module which consisted of a verilog a model of a counter some vpulse sources and it was working. I was wondering if a verilog ams module can use a vector file as a stimulus with connectlib files selected to determine the logic levels. So far it doesn't seem to be working. Can vec files only work with actual device circuit models or do they work with functional and verilog ams cell views. I am attaching a picture of the test b nch with the module and the vector file, so that if I made a mistake, someone here can catch it.