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RE: APS/Spectre simulation data too big

thx!

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net, terminal, signal

Hi, I'd like to change label names including pin names after selecting labels and pins that I want to change. A skill code changing text is done but I should add more lines to change pin names as well...

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RE: Vector files and verilog ams modules

I won't bother moving it - just as easy to answer here. Vector files (and VCD files) can only drive analog nets, not digital nets in a mixed-signal simulation. You'd have to stick a resistor (say)...

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RE: Cadence Virtuoso Simulink Co-simulation

Yes, that's still supported. The video talks about this being between spectre and simulink (which does also exist) but what you're actually seeing in that video is a AMS-Simulink co-simulation. I gave...

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RE: EM/IR Analysis Setup missing from ADE L menu

Actually, Andrew just checked that EMIR form was introduced in IC6.1.6-64b.500.7. But I will suggest you move to the latest IC and Spectre (MMSIM) versions if possible to be able to access all new EMIR...

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RE: overlaping due to transition function verilogA

Here's a more concise version of the model above, just because I thought it was a bit verbose. Essentially does the same thing though: `include "disciplines.vams" module nonoverlap (s4,s5,s6); output...

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RE: how to display refdes rats on manufacturing-assembly drawing

Enable the user preference under Placement - General called display_refdes_rats then this are shown as part of the Refdes\Assembly_top layer so make sure that is turned on.

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RE: Unable to import psm path

So the padstack has a shape symbol as part of it and PCB Editor cannot see that file. Make sure that any filename.dra and filename.ssm are available in your psmpath. Personally I tend to keep dra and...

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How to start multithread

I am building a skill which perform a heavy calculation. Does any body know how to start multithread to calculate parallel. Just like running DRC in allegro. Seems it start multithread to run the DRC

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RE: Vector files and verilog ams modules

Thanks, Andrew for the quick response. Is the discipline resolution influenced by the presence of verilog A models and analog sources like a pwl source? If I use a connect module instance and just...

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RE: how to automatically select the content of a field when a form appears?

Thanks Andrew, I’m using the IC617isr15, And I have tried the function hiSetCurrentField(), but it seems doesn’t work well at all times . Below is my major script, could you please help me to find the...

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RE: how to automatically select the content of a field when a form appears?

The code didn't quite work because the arguments to hiCreateAppForm are incorrect. I tried a number of things, and I think you can't do it when the form is created. You can however do it on subsequent...

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Uncheck update instances in rename cell dialog

Is there a way to uncheck the Update Instances box in Rename Cell dialog by default (eg. in .cdsinit)?

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RE: net, terminal, signal

Thanks Max, I understand a terminal can be a port of schematic having a net and being not an internal net. Am I understanding in the right way?

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RE: net, terminal, signal

Thanks Andrew for explaining what signals are. I had hard time when I should edit tons of net names like nets A by hand due to schematic change. So I wrote a skill code editing label's names at a...

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RE: Unable to import psm path

Thanks Steve I tried putting the dra, psm, and pad into the same folder perfectly flat, but after exporting it still puts an error and when placing the symbol in Allegro 17.2. Is there a file other...

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Multiple flight wires to symbol terminal

While placing more than a single flight wire on a terminal in layout, moving the instance will cause the flight lines to remain in the same place, but the connected terminal will create a wire going...

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RE: EM/IR Analysis Setup missing from ADE L menu

Hi, Thank you very much for your help. I will move to the latest IC and Spectore(MMSIM) so that I will be able to see the EMIR from in ADE. Regards, yyama

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Sigrity 2018—Into the 3rd Dimension

Cadence has talked about System Design Enablement for the last few years, taking a more holistic view of designing a system. This means taking into account not just the chip(s) in the system, but also...

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RE: Vector files and verilog ams modules

I was playing around with it a bit more. Will it work if I attach resistors at the input and output buses like below? I am attaching my vector file as well. The waveforms I get are wrong. The inputs...

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