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RE: Vector files and verilog ams modules

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I was playing around with it a bit more. Will it work if I attach resistors at the input and output buses like below? I am attaching my vector file as well. The waveforms I get are wrong. The inputs don't seem to change after every 10ns but seem to stay the same for the entire length of the simulation (0,0). I get the right output but was wondering why the inputs don't change.

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