Hi All, Wondering, whether it is possible to simulate a *.vams generated from ADE-L (using AMS + ultrasim) in DoT flow? To explain, I have a schematic which has both digital and analog components, so I had to use AMS for netlisting. Now since my design is complex block, i Would like to use verilog testbench to reduce testbench development time, for each case. Is it possible to do? any hints? if not, could anyone suggest me any better way to use script based testbench. Initially I was using VCD for doing the same, VCD has no issues with pure analog simulation. But When I change my simulator to AMS, the signals that are represented by bus (e.g: S ) all ends up floating nodes. I do have alias [*] setup in my vcd control file. As I wasn't able to fix it. I had to move to DoT flow and I am not sure whether it will work or not. any suggestions or ideas? Thanks! Aarthy![]()
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