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RE: Request - Skill script for block level floor planning (Constant area...
Carona, The soft blocks has this functionality of constant area stretch. You can create a new cellview with only a prBoundary, you set the CellType of the cellview to blockBlackBox, you save it. Then...
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RE: Request - Skill script for block level floor planning (Constant area...
Ah, thanks Alex. Shows what happens when I don't read the title of the request and focussed too much on the text where it was talking about stretching polygons and rectangles. I missed the...
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RE: Convergence problems using analogLib switch (DC simulation)
Pedro, Please can you post the top level netlist (i.e. all the instances of the relay component and so on) - don't necessarily need to see the rest of the hierarchy (unless you're happy to share them)...
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RE: Meaning of the "Event Time" in Direct Plot form of Pnoise Jitter
Dear Andrew, Thanks a lot. It is indeed the case. One more thing, for plotting Jee, Jc it asks for Integration of Frequency Limit. I am little bit confused of what range should be given as Jee and Jc...
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RE: Convergence problems using analogLib switch (DC simulation)
Hi Andrew, Thanks for replying. I removed all the relays,except one, and it doesn't converge. However, if I put back the other 2, it converges. :-| But, when using all the 3 sources, the pulse signal...
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RE: Shape to Thu Via Spacing
Looks like you are using shapes for the tracking, might be better to use clines but in any case this is an issue because the via has a different netname to the shape. In 17.2 latest hotfix hover ver...
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RE: Liberate_AMS for .lib generation.
Hi, I'm using Liberate_AMS for characterising an AMS block....Even though my desired arc is getting characterised, the log file is getting filled with the error message attached below: I'm attaching...
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Ajit and the History of SEMI
At SEMICON China, there was a press briefing with Ajit Manoja, the CEO of SEMI, along with Lung Chu, who runs SEMI China, and thus also has responsibility for SEMICON China. This year was the 30th...
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RE: Annotating Ref Des in schematic yet not impacting Layout parts
You could set the Auto Rename flag in the PCB Editor Configuration Manage to allow changes to only those parts you want to update. Then you can specify how you want the parts renamed before you run the...
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RE: Request - Skill script for block level floor planning (Constant area...
I appreciate all the help, I noticed that command in the drop down menu, but never knew how to use it. Thanks again.
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RE: OrCAD16.6 DRC check problem: "Net has two or more aliases"
Hi, Edit the symbol to change the pin type to 'Passive'. This makes the pin name no longer a signal alias.
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RE: Convergence problems using analogLib switch (DC simulation)
Hi Andrew, I swapped vt1 and vt2, as you said, re-named en_pulse, en_sine, en_step back to "stimuli" and hanged a 10k resistor from "stimuli" to ground. And .. it is working now :-) Thank you very much...
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RE: Void in Place Bound Layer
You could define two shape, add an arc on the edge and place them next to each other. You can even have them overlap if the arcs are a little tricky to add to the edge. If you don't want to play with...
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constraints: MIN_METAL_SPACING and MECH_PIN_TO_CONDUCTOR_SPACING
I'm having trouble locating these constraints. I want to change the hole to everything spacing to 30 mil. I did it in constraint manager but when I update the dynamic planes the spacing is still 8 mil....
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RE: Void in Place Bound Layer
I tried creation on the copper layer and then Z-copy to Place Bound, but it threw away the void. Not sure if I'm doing it incorrectly. Abutting shapes with arcs worked, so I guess that's the winner. I...
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RE: Post layout simulation using Ocean Script
Hi Dimitra, Yes, I have included the extracted view and included it in the 'Switch View List' as you mentioned. As far as i have understood and verified till now is that when you include the extracted...
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Spectre simulation of verilogA file
Dear All, My schematic consists of a dc voltage source and a simple resistor written in verilogA, just to understand how to use verilogA files with Virtuoso ADE. The netlist from Virtuoso ADEL ->...
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RE: constraints: MIN_METAL_SPACING and MECH_PIN_TO_CONDUCTOR_SPACING
In Constraint Manager, Analyze>Analysis Mode(s), Design, General is where these parameters are located.
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