Dear All, My schematic consists of a dc voltage source and a simple resistor written in verilogA, just to understand how to use verilogA files with Virtuoso ADE. The netlist from Virtuoso ADEL -> Simulation -> Netlist -> Display is as follows: // Generated for: spectre // Generated on: Mar 23 01:58:58 2018 // Design library name: labs // Design cell name: testing_verilogA // Design view name: schematic simulator lang=spectre global 0 // Library name: labs // Cell name: testing_verilogA // View name: schematic V0 (net2 0) vsource dc=1.2 type=dc I0 (net2 0) resistor_verilogA r=1 simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf dc dc dev=V0 param=dc start=0 stop=1.2 write="spectre.dc" oppoint=rawfile \ maxiters=150 maxsteps=10000 annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save I0:in saveOptions options save=allpub ahdl_include "/home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va" After running the dc simulation, the error in my Virtuoso CDS.log window is: ERROR (ADE-3036): Errors encountered during simulation. The simulator run log has not been generated. Possible cause could be an invalid command line option for the version of the simulator you are running. Choose Setup->Environment and verify that the command line options specified in the userCmdLineOption field are supported for the simulator. Alternatively, run the simulator standalone using the runSimulation file in the netlist directory to know the exact cause of the error. So I went to my netlist directory from my terminal and used the ./runSimulation command. The resulting output is as follows: Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: sv376 Host: en-ec-ph314-10.ece.cornell.edu HostID: FD80C911 PID: 31974 Memory available: 6.5414 GB physical: 16.5123 GB Linux : Red Hat Enterprise Linux Server release 7.4 (Maipo) CPU Type: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz Socket: Processors [Frequency] (Hyperthreaded Processor) 0: 0 [3576.1] ( 4 ), 1 [3850.0] ( 5 ), 2 [3856.1] ( 6 ) 3 [3949.8] ( 7 ) System load averages (1min, 5min, 15min) : 1.2 %, 1.9 %, 2.9 % Hyperthreading is enabled Simulating `input.scs' on en-ec-ph314-10.ece.cornell.edu at 1:59:53 AM, Fri Mar 23, 2018 (process id: 31974). Current working directory: /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist Warning from spectre. WARNING (CMI-2015): Unable to open log file `../psf/spectre.out'. Success. Reading file: /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist/input.scs Reading link: /opt/cadence/mmsim Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg Reading file: /usr/include/stdc-predef.h Reading file: /home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams Time for NDB Parsing: CPU = 46.849 ms, elapsed = 127.028 ms. Time accumulated: CPU = 58.888 ms, elapsed = 127.031 ms. Peak resident memory used = 31.4 Mbytes. The CPU load for active processors is : Spectre 0 (30.8 %) 1 (7.7 %) 2 (7.7 %) 4 (7.7 %) 6 (8.3 %) 7 (9.1 %) Other Error found by spectre during AHDL read-in. ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB/ (775) ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB//.resistor_verilogA.ahdlcmi/ (775) ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/ (775) ERROR (VACOMP-2252): Cannot open file: input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/resistor_verilogA.lst - C-code will not be generated !!! Reading link: /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/discipline.h Reading link: /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/constants.h Time for Elaboration: CPU = 19.989 ms, elapsed = 25.1319 ms. Time accumulated: CPU = 78.993 ms, elapsed = 152.279 ms. Peak resident memory used = 38.1 Mbytes. Aggregate audit (1:59:53 AM, Fri Mar 23, 2018): Time used: CPU = 79.1 ms, elapsed = 152 ms, util. = 51.9%. Time spent in licensing: elapsed = 14.6 ms, percentage of total = 9.56%. Peak memory used = 38.2 Mbytes. Simulation started at: 1:59:53 AM, Fri Mar 23, 2018, ended at: 1:59:53 AM, Fri Mar 23, 2018, with elapsed time (wall clock): 152 ms. spectre completes with 4 errors, 1 warning, and 0 notices. At this point, I have tried web searches and the forum and to see how to resolve 'unable to create directory ....' errors that occur above. Why is spectre unable to create the above directories? How can I resolve this issue? I appreciate any help I can get. Thank you! Regards, Krishnaa![]()
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