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Converting an Allegro brd file to ASCII
I have a Xilinx Zynq demo board Allegro brd file from around 2013 that I would like to convert to a format readable with Altium Designer. The Allegro ASCII format is supposed to be compatible to some...
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cadence chip assembly autorouter drc error
Hi, I am using cadence version IC6.1.6 to design in soi45nm technology. I have a drc rule file to be used with calibre nmDRC but it does not support assura. When I tried to run chip assembly router for...
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RE: Cross talk analysis
Hello, I see that these *crosstalk do files* postings are over 10 years old. Has this changed? What is the latest version of the best method to enter crosstalk rules into Allegro? Thank you
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The Promise Of Digital India
By 2019, it is estimated that there will be five billion mobile phone users in the world, with around 67% of the world’s population owning a mobile phone, according to the website Statista. In India,...
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TSMC 30 Years Ago Today
At IEDM in December, Gary Dagastine is one of the people responsible for press relations for the conference. My piece about Chips and Technologies, the First Fabless Company reminded him that back in...
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Cannot start ncsim when launching ams simulation
Hi all, I got a problem on mixed signal simulation using MMSIM 15.2 and INCISIV 15 When I have configured the MMSIM and INCISIV package, I start to run a tutorial called "vfs_amsflow" I could...
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Changing Flex material in Allegro PCB Designer 17.2
Hi, I am using Allegro PCB Designer 17.2 and i'm designing a Rigid flex board. There are few problems which i am facing in this design. 1. After adding the multiple stackup say Flex1 and Flex2 along...
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LMtools not detecting Virtual adaptor MAC address
Hi, I got my license generated on my Virtual Adaptor MAC Address. Now the LMtools is not detecting this MAC ID,it doesn't show up in Ethernet address under system systems of LMtools and i'm getting...
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RE: Cannot start ncsim when launching ams simulation
Hi James, I can't find any reports of the same problem (at least nothing recent). I'm not sure it's related to the GCC version mismatch (that may be a diversion) - may be related to a permission...
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Open ADE-XL in graphical mode via SKILL
Hello, is there a SKILL command to open a ADE-XL view, so that a new ADE-XL window will be shown? So basically I need the underlaying SKILL command when someone double-clicks on a ADE-XL view in the...
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RE: Open ADE-XL in graphical mode via SKILL
Ok, I found it out myself.It can be done using e.g. geOpen(?lib "myLib" ?cell "myCell" ?view "adexl") .
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I want to assign an element of list to some pointer/attribute to access that...
Hi , I am using following procedure to have a result I needed in list format....
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RE: LMtools not detecting Virtual adaptor MAC address
There won't be any resolution if the license manager cannot find the MAC address, it is required and FlexLM licensing won't go any further without it. You could try the debug.log file for the license...
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Differential Pair to Pair Spacing
I want my diff pairs set up as follows. (8 layer PCB) Allegro 16.6 Top and bottom 5.5mil width with a 10mil space L3 and L6 5mil width and a 7mil space I need 30mil PAIR TO PAIR PROBLEM: When I set 30...
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RE: Changing Flex material in Allegro PCB Designer 17.2
Assuming that you are in Multi Stackups Mode in the Cross-section editor, All Stackups tab lists the layers and the "tick boxes" determine what layers are, or are not, in the particular named...
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RE: I want to assign an element of list to some pointer/attribute to access...
Raghu, Not really. You always refer to a sub-list and then access that again and again - so entry=car(yourResult) - then you can you use car(entry) or cadr(entry) - so you don't need to find the...
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RE: Differential Pair to Pair Spacing
Add a Net Class Class for the Diff Pair Class to Diff Pair Class and apply the required Spacing rule to the CCls in Spacing.
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RE: Help, Corner Analysis doesn't work in vco, error in evaluating the...
I don't really understand what your problem is. You say the expression evaluates correctly - but then say "its corner analysis is not working". What does that mean? Please give more details - perhaps...
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RE: cadence chip assembly autorouter drc error
Hi Supriyo, The Chip Assembly Router does not use Assura (or Calibre) rules, so having Assura rules won't fix the problem anyway. It uses information in the OA technology database (in your technology...
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