I want my diff pairs set up as follows. (8 layer PCB) Allegro 16.6 Top and bottom 5.5mil width with a 10mil space L3 and L6 5mil width and a 7mil space I need 30mil PAIR TO PAIR PROBLEM: When I set 30 mil as my min space I get DRC's within pairs because their spacing is 7 or 10. I only get this problem on layers 3 and 6, Top and bottom diff pairs route as expected 10 mil space and 30mil pair to pair. Any ideas?![]()
↧