Hi Supriyo, The Chip Assembly Router does not use Assura (or Calibre) rules, so having Assura rules won't fix the problem anyway. It uses information in the OA technology database (in your technology library) to define the minWidths, minSpacings and so on for each layer and interactions with layers. It suggests that maybe your technology library is incomplete - so you either need to contact the foundry who provided the technology database, or go through your university programme. If in Europe that might be Europractice - don't know where you're based. Regards. Andrew.
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