Hi, I am using cadence version IC6.1.6 to design in soi45nm technology. I have a drc rule file to be used with calibre nmDRC but it does not support assura. When I tried to run chip assembly router for automatic routing, there were many drc errors on the finished layout. I am guessing it might be because virtuoso chip assembly router uses default design rule file and therefore not consistent with the rules used by calibre. Can anybody offer any insight into this. What should be the approach to convert calibre drc rule set to assura so that I can run assura drc or is there other way to get around this problem. I am also thinking if it would be possible to guide the auto router to use calibre drc rules. So far I know that my university does not have assura drc rule file for soi45nm technology. Thanks Supriyo![]()
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