Clik here to view.
OrCad Captur CIS - How to replace to a new Title block with while keeping the...
Hi, I have a new Title Block that I want to update in my already existing designs. Is there a way to replace the Title blocks while keeping the data in the fields from the original Title Blocks on each...
View ArticleClik here to view.
RE: How to get via Constraint
Hi Andrew, I have some related question about viaGenerateVias* functions. It seems that it can only handle top level. How do I use them to fill via in the lower level of a cell. Thanks, Yanhong
View ArticleClik here to view.
Printing to a file using fprintf
Hi, I have a simulation for generating MOS transistor data using a 4 nested sweeps (VGS, L, VDS, VSB) for a 4-terminal NMOS device. I am able to setup the simulation and run it with all working OK....
View ArticleClik here to view.
Clik here to view.
How to change routing configuration in Power Routing Options form in Virtuoso XL
I'm using Virtuoso 617. I am trying Route->Power Routing feature . The Power Routing Options GUI form (with Block Ring tap is choosen ) is pre-defined with "Horizontal Routing Layer" = "M1 M3 M5 M7"...
View ArticleClik here to view.
flip-flop issue in Capture
Hi all I'm running simulation which involves a flip-flop. Problem is t he output of the flipflop stays low in this particuliar circuit no matter the input is. I checked the setting for CLR and CLK in...
View ArticleClik here to view.
Evaluate expression only after all parametric simulations are finished
I'm using ADE Assembler (IC6.1.7-64b.500.17). I have a parameterized desgin variable. I have an expression for the noise and for a certain current. The noise and currents are both calculated/evaluated...
View ArticleClik here to view.
RE: Cadence Liberate Characterization Help
Hi Cao, I am not getting any error and characterization was finished successfully. None of the cells are listed in 'List of failing cells'. I have made the changes as you suggested but I am still...
View ArticleClik here to view.
RE: Specman Mode for Emacs
ขอบคุณมากครับสำหรับความรู้ เป็นประโยชน์ มากๆ เลย ufabet http://www.ufa007.com/ufabet :AO
View ArticleClik here to view.
RE: Model Selector question
Thanks alokt, I was refering to [Model Selector] keyword in the IBIS standard. When the component model contains more than one vesion inside the ibis file i.e. 1.8V 2.5V 3.3V the assingnment is always...
View ArticleClik here to view.
RE: WARN MESSAGE: (IMPESI-3014): The RC network is incomplete for
Hello Andrea, Are you getting these messages during the hold fixing iteration? If you run "timeDesign -postCTS" on the DB, do you see similar messages? If it is seen during hold fixing step it could be...
View ArticleClik here to view.
Clik here to view.
RE: Innovus NanoRoute Errors with LEF DEFAULT constraint group
Hi Rob, Kindly check on the following App Note: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050SIEAY&pageName=ArticleContent&sq=005d0000001T5yuAAC_2018103103335758...
View ArticleClik here to view.
Genus - Segmentation Fault
Hello everyone, I am trying to do large-scale Genus RTL synthesis in our new server. But I get Segmentation Fault while doing that. At above you can see the end of my genus.log file. I change...
View ArticleClik here to view.
RE: WARN MESSAGE: (IMPESI-3014): The RC network is incomplete for
Hi Chetan, yes it's durine postCTS hold fix. Do you mean that the tool have an "old' version of netslist before the fixing, and try to extract a "gost" net?
View ArticleClik here to view.
RE: Evaluate expression only after all parametric simulations are finished
Hi Andrew, I swept a design variable (used in several CDF fields in multiple components). Changing the EvalType to sweeps solves indeed the problem that the expression is evaluated for each single...
View ArticleClik here to view.
The Day a PCB Was Born
By John Burkhert Jr I want to take you back to a project that highlights a few twists as all good projects will. 17 years ago I was presented with 20 pounds of potatoes and a 10 pound bag. The bag was...
View ArticleClik here to view.
RE: flip-flop issue in Capture
this model doesn't have PREBAR, and the CLRBAR is set to 1. Input singnals are just fine, at least in PSpice AD
View ArticleClik here to view.
RE: How to get via Constraint
Andrew, I mean fill via in the overlapping regions in lower levels of hierarchy. I tried to use ?startLevel and ?stopLevel argument as you suggested, and it worked. Thanks a lot, Yanhong
View ArticleClik here to view.
RE: compare pins from 2 symbol
Hi Andrew, I mean by comparing pins: a list of differences in number of pins, pin's name, pin's direction and pin's signal type. Thanks, Rose
View Article