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RE: flip-flop issue in Capture
hi alokt I found the cause. The output of 74175 was connected to a net taking STIM signals. It must have been STIM forcing the flipflop to stay low all the time. thank you for reply!
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RE: Cadence Liberate Characterization Help
Hi Cao and Anuradha, Thank you for your suggestions. It seems like I can generate the .lib file successfully using the fictitious model file provided with the tool. However, whenever I am using NCSU...
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AMS simulation on a synthesized netlists --- NO sim result
Hi there! I am trying to run ams simulation for a big design mixed of digital and analog. However, the output of simulation for the digial block is always tied to zero and basically there is no output....
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Breakfast Buffet for September 2018
https://youtu.be/aWnEDVUQwoY The three highlighted posts for August were: The New Tensilica DNA 100 Deep Neural-network Accelerator CDNLive India Ambit Design Systems Sign up for Sunday Brunch, the...
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What's For Breakfast? Video Preview October 8th to 12th 2018
https://youtu.be/0CNhCWOxPKY Coming from TSMC OIP Ecosystem Forum, Santa Clara (camera Seena Shankar ) Monday: The History of ISO 26262 Tuesday: ESD Alliance Digital Marketing Workshop Wednesday:...
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Should memory macros provide a SITE definition?
We're having a debate amongst a few engineers as to which is better: LEF for a memory macro should not have a SITE, or... LEF for memory macro should define a unique SITE Please help us. We'd like to...
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RE: Innovus NanoRoute Errors with LEF DEFAULT constraint group
Chetan, Thank you for providing this app note. I resolved the issue by using the guidance from page 7, setting the parameter "setGenerateViaMode –auto true" prior to loading in the design. My design...
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RE: Re-annotate Schematic after Layout
Sounds like you are failing to back annotate. Do that before doing any forward annotation and you will be fine
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RE: Issues with nanoroute Soc Encounter
Hi Bilal! I have the same issue. Have you solved it?
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RE: Innovus NanoRoute Errors with LEF DEFAULT constraint group
Hi Rob, Good to know that the issue is resolved with the suggestions in the app note. Please do visit http://support.cadence.com to get any help on Cadence tools. Regards, Chetan B S
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RE: how to sweep an equation which is formed using variables?
Yeah, I agree with your approach but in case if I don't want to fix any one of the variables and sweep the ratio. Is there anyway? Its like if I have three variables x,y,z and there is a relation...
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RE: AMS simulation on a synthesized netlists --- NO sim result
Hi, This will be much easier to resolve if you contact Cadence customer support. It can be difficult to guess the problem based on a simple description of the setup. Regards, Saloni
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RE: how to sweep an equation which is formed using variables?
No. This is not possible and I can't see it would make any sense either given that there would be no constraints on any of the variables - there are multiple solutions to that equation if you are just...
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RE: Cadence Liberate Characterization Help
I can not find out the reason with what you have provided. It could be some problems with your input data or the settings. Also, please try -extsim spectre option in your char_library command. If you...
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PCB West: History of PCB
At PCB West recently, Wally Rhines gave one of the keynotes. It was titled Is Past Prologue? The Future of the PCB Design Industry . Wally said that it wasn't really his title, it was given to him by...
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ADE-XL - How to make use of licenses more efficient?
Hi, I am simulating hundreds of corners for more than 10 tests on ADE-XL and I need to optimize the use of licenses as much as possible. When running tests sequentially in series, all my licenses are...
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Error in layout extraction
Hi, I am trying to check the DRC for my layout design, when I run DRC I got this error with the following message: sh: -c: line 0: syntax error near unexpected token `(' sh: -c: line 0: `cp...
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RE: Error in layout extraction
This is a Mentor tool that you’re using, so asking a question in a Cadence forum is not the best place to ask. I would suggest either a Mentor forum or Mentor customer support. Regards, Andrew
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EXTRA: Did the Chinese Really Attach Rogue Chips to Apple and Amazon's...
Today, Bloomberg's BusinessWeek (BW from now on) published a story The Big Hack: How China Used a Tiny Chip to Infiltrate US Companies . The big question is whether they actually did or not. If they...
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Allegro Design Entry Hdl PM Error
this error is shown when a project is opened even if i am using libraries from local directory not from cds_site. i am using Design Entry HDL 17.2 Hotfix S046. Regards, Jesh
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