Full OSSHNL error list
Hi, Occasionally we get error message: ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again....
View ArticleNC-verilog Executable blank
Hi, When working with NC-Verilog, we get “executable” blank error. In the forum there are also post1 , post2 which suggest it is related to INCISIV installation. So is it imperative to install INCISIV...
View ArticleRE: NC-verilog Executable blank
Hi, You will need to install INCISIVE as you want to use a digital simulator. Regards, Saloni
View ArticleRE: Restrict innovus tool in placing VIABAR
Sounds like you have a situation where there is wider metal that requires a double-cut (or more) via instead of a single-cut. There are usually rules in the LEF file that say what metal widths need...
View ArticleRE: how to delete via cell in the design
I don't think you can delete an NDR during an innovus session. You would have to edit the tech LEF then reread the design in a new session, making sure that the NDR you deleted is not used anywhere in...
View ArticleRE: Hold Timing Violations
look into the use of scale factors pre/post route... or run signoff QRC earlier in the flow.
View ArticleRE: Hierarchical flow with (some) manual place and route
I believe you can still use Innovus - you will have to have LEF models for these other blocks, or if they really are black boxes, they can be defined as such early in the flow, but you'll want LEFs for...
View ArticleRE: Padring Routing
usually the padring is connected by abutment, meaning the simple act of having the pad cells placed together in a ring is what connects the padring, provided you have IO fillers in any gaps, and corner...
View Articleencounter invoke rc executable?
Hi, The rc command, found in socencounter/bin folder, as described in rc_user.pdf, provides many basic functionalities. The SoC Encounter program, when we click Design>>Import RTL, does it...
View ArticlePlayground Timing lab and constraint?
Hi, We would like to get familiar with some basic steps in encounter design. If we want to import some most simple Verilog in encounter, it asks for Timing lab and constraint. Is there any default Lib...
View ArticleRE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Hi, Any progress on the above issue? Regards
View ArticleRE: Noise Figure of LNA with an input tone (using hb/hbnoise)
No. To be honest I wasn't planning to as I had really explained the root cause - figuring out why it was not showing with the LNA in the workshop was rather secondary. Almost certainly it's something...
View ArticleRE: Full OSSHNL error list
No. The main purpose of the error codes is to help us track down precisely which bit of code is generating the error; the goal is that the error message is self-explanatory (in fact the wording was...
View ArticleRE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Hi Andrew, sorry for the misunderstanding. I thought that you will have a look on that and post your findings. Anyway, thanks for finding time to answer. Regards
View ArticleHow can stop gerber data release with same name in same location in allegro...
I am using Allegro 16.2 . I do not want to release Gerber data with same name ( I have already used) in same location.How can do that?
View ArticleEDA: Not Like Household Products
I wrote recently about why EDA sales are not like semiconductor equipment sales, despite having a lot of the same customers, and the same Moore's Law process technology treadmill. But EDA isn't like a...
View ArticleDigital Twinning, Explained: You Won't Believe the Metaphor This Time
It makes sense, right? When developing an expensive hardware/software system—think cell phone, server, car, or fighter jet—you might want to make a virtual model alongside it to make sure that it works...
View ArticleRE: 3D Canvas Viewer not bending PCB with proper radius
FYI, this is a bug. I reported to Cadence and they have checked in a fix to be released with a future hotfix.
View ArticleRE: Generating shapes of overlap of two layers within multiple hierarchies
Hey Everybody, Thank you for the input everyone. Sorry for the late update, I was able to get my script working but got bogged done with adding features. My version of Cadence is 6.1.6 so I...
View ArticleRE: RE: Electromigration SEB flow FIT calculation
Hi, in that case, please contact Cadence customer support for further information on Voltus-Fi support for FIT. Thanks, Saloni
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