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Footprint naming for like footprints with different pins missing
Are there industry-standard guidelines for naming footprints which are otherwise similar but have different pins missing? For example, take a look at the package options at...
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Assura LVS: different nets in pad's schematic (vdd3r) and it's layout (vdd3r1...
Hi, I am using 3.3V PADs (in AMS 0.35) which have different nets in schematic "vdd3r" and in layout "vdd3r1 & vdd3r2" which these two nets are shorted in layout. I used net set in schematic and...
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modgen: best way to change device m-factor?
Hello, The following question does not have a clear answer for me after reading some of the Cadence documentation on modgen. I have been using modgen only recently and find it very useful, but wondered...
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RE: Form checklist question
This wouldn't really work if you had more than one checklist group. I don't see a way to grab the group a field is associated with in SKILL. Less elegant method would be writing a function that passes...
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Preserving color when flattening
Suppose I have an instance with the mask1Color locked property on some shapes. I do not see an option to leFlattenInst() (or in the GUI) to preserve said property. Can/should this be added some day?
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Generating shapes of overlap of two layers within multiple hierarchies
Hi Everybody, I am trying to generate shapes that are the overlap of two layers in a layout cellview. The cellview could contain additional levels where I would have to bring those shapes up to the top...
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RE: Connecting component body to ground on smd board
Well very good and I'm glad you got it figured out The same net constraints are just a little hidden Gem in Allegro - I'm not sure Gem would be the best word as believe me they can cause some pain, in...
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RE: Generating shapes of overlap of two layers within multiple hierarchies
Hi Quincy, Try abe* functions (ABE => Advanced Boolean Engine) -Ramakrishnan
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how to measure corner frquency in verilogA
Hi, I want to access a node voltage (in AC sim) and measure the 3db frequency in verilogA , please help me with the syntax. Here the motivation is use this info and adjust some trim bits to tune the...
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question on acmatch sim in spectre
Hi, I use 'acmatch' analysis to get sigma of voltage in AC analysis. Here I have a special case where I need to find it for a difference in AC magnitudes like: mag(V1) -mag(V2) using a vcvs in the...
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RE: problem with lvs in calibre
i dont have access to mentor graphics company because its not in my country but thank you for your kind response
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RE: "Incorrect Instance Error" while running LVS
hi i have the same problem can you tell me how you solved it if you are still available ?
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*WARNING* Connection to MACHINE failed. No route to host
Hello, when I want to start PVS in the Virtoso Layout Editor I get the warning *WARNING* Connection to MACHINE failed. No route to host in the CW . (MACHINE=name of the machine on which I started...
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Temporals, Reset, and Test Phases
One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset...
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RE: *WARNING* Connection to MACHINE failed. No route to host
Matthias, Not sure. Best would be to contact customer support . First thing I'd check is what /etc/hosts contains on the machine in question (perhaps you can post it here?). Regards, Andrew.
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RE: how to measure corner frquency in verilogA
You can't do this in VerilogA (you can't really create frequency-domain descriptions, and certainly not this kind of measurement). Typically such a test of a calibration loop would be done with the ADE...
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RE: Preserving color when flattening
Tom, There's no option to do this because it does it anyway without an option. It's mentioned in the documentation for dbFlattenInst/dbFlattenInst2 and leFlattenInst. BTW, asking for something to be...
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RE: question on acmatch sim in spectre
I don't think this is possible (from a few quick experiments of an idea to workaround it). You should contact customer support - might need an enhancement to spectre. Regards, Andrew.
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best resources and RAKs on Verilog A, Verilog AMS and AMS designer, ADE...
Hello, As the thread title implies, I was hoping someone could point me in the right directions as to what are best resources on Verilog A, Verilog AMS design on the support site. Any RAK which servers...
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