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RE: MonteCarlo simulation is taking much longer time than expected
Do you have more than one corner enabled? Or corner and nominal? Perhaps a screen shot would help... Andrew.
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RE: MonteCarlo simulation is taking much longer time than expected
H Attached is the snapshot. Also I want to know whether it is becoming slow because of many output parameters to be evaluated as shown in the snapshot ? I have attached the generated the oceanScript...
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RE: MonteCarlo simulation is taking much longer time than expected
OK, there are 200 runs because you have 100 monte carlo points but two corners - nominal (which is the default test model setup) and corner C1. So that's 2*100. As for the number of outputs, it's not...
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RE: VerilogA model Monte Carlo Simulation - Histogram Curve
Hello Andrew, I understand that this example varies the parameter r with monteres as mismatch parameter ( r_effective = r+monteres ). We are able to get the histogram for the op by using the expression...
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Veriloga parameter expression
In veriloga documentation I have seen examples where one parameter is used to set the default of another parameter in the same module. When I tried this I found it didn't work in ADE/spectre. A simple...
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RE: Lisp in Eclipse
Hi sm27 I think this is not the right forum for this question. Perhaps you might want to try a Lisp or Eclipse development forum. Best regards Quek
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RE: more pin name and net name checking at check and save
Hi Enzhu You can use schRegPostCheckTrigger function to automatically execute a SKILL procedure after check&save. Please see $CDSHOME/doc/skcompref/skcompref.pdf. Best regards Quek
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RE: Leakage current and Leakage power
Hi Sanjay24 You can use XPS to do the leakage check. Please search for "SRAM Leakage Current Simulation" in $SPECTREHOME/doc/spectreuser/spectreuser.pdf. Best regards Quek
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RE: Connecting component body to ground on smd board
Hi, Generally speaking you would connect to the ground plane using vias. What is the Regulator P/N you are using. Paul.
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RE: Grid spacing in schematic part editor
Nope. It has a fixed grid spacing. In thinking about this it is probably because when you place a symbol on the schematic you would want it's pins to land on the grid so that they could be wired up. In...
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RE: VerilogA model Monte Carlo Simulation - Histogram Curve
Hello Andrew, I got it by writing the expression VDC("/op") / IDC("/V1/MINUS")). Please suggest whether we have any other way of plotting it. Thanks in advance Regards, Vijay
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RE: Veriloga parameter expression
Dear Robin, Please refer the work around proposed by Andrew . I think you need to do the following steps Tools->CDF->Edit, pick "Base" CDF and edit the CDF of your cell (the one with the VerilogA...
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RE: VerilogA model Monte Carlo Simulation - Histogram Curve
Vijay, I first misread what you wanted and so did some screengrabs on how to plot a histogram of the statistical parameters monteres . So I'll show that in case it's useful, then explain how to get a...
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RE: Veriloga parameter expression
Vijay, Robin, Note, you don't need to delete the parameter (in fact it's not the myres parameter that's really the problem). When the CDF for the component is created, it creates two CDF parameters...
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ADE XL netlisting error (some schematic components are blank)
I have a simulation that isn't working with ADE XL - whenever it netlists parts of the netlist have no connections. I am using standard cells with predefined connections in them and have some schematic...
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RE: more pin name and net name checking at check and save
In addition to the function that Quek mentioned, there's also some newer infrastructure (which has existed since IC615 - so for the last 7 years) to define custom checks which update markers and can be...
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RE: ADE XL netlisting error (some schematic components are blank)
First thing to check is whether you have Analog netlisting mode enabled. Type: cdfGetNetlistMode() in the CIW - it should return "Analog". If not, before you start virtuoso enter: setenv...
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RE: ADE XL netlisting error (some schematic components are blank)
Thanks; yeah think I'll go through the support channel so I can send things over. That being said - when I run the command cdsGetNetlistMode (assuming it was CDS given the environmental variable and...
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RE: Grid spacing in schematic part editor
Thank you for the quick reply Paul. Now I understood why it isn't allowed Regards Chadga
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RE: Veriloga parameter expression
Vijay, Andrew, OK thanks, blanking the default for the derived parameters fixed the problem. I found I would need to do the CDF edit again if I changed the VerilogA, even just adding some comment...
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