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RE: BB Via Net name report
try changing the output section of your code to the following to not output vias spanning from Top to Bottom: foreach(via allViasInDesign when(or(not(nindex(car(via->startEnd)...
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RE: No DC solution found (no convergence)
Dear Sir As you have mentioned we are colleagues and we are working on the same group. I am really stuck at DC analysis. I need it to find static power dissipation. As I have mentioned earlier I am...
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RE: No DC solution found (no convergence)
I doubt it will be possible to debug this from just a segment of the log file alone (you didn't include the whole log file, so I don't even know which version you're using). it seems rather odd that a...
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problem in UltraSim simulation
hello guys. I am using IC 5.10.41. When I used UltraSim simulator to run simulations on digital circuits, the simulation completed successfully but all the digital output voltages were 0; I checked the...
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RE: problem in UltraSim simulation
Presumably you either have empty schematics for these cells (just the pins) or have included an external reference to these cells which are missing the contents. Without knowing what your simulation...
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RE: schCheck(cv) warnings and errors after updating CDF params
Hi Andrew, Thank you very much for your response. We are using TSMCN5 PDK. I did do what you suggested and the errors and warning went away! Done updating CDF INFO (SCH-1170): Extracting "MY_SCHEMATIC...
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RE: schCheck(cv) warnings and errors after updating CDF params
[quote userid="440995" url="~/cadence_technology_forums/f/custom-ic-skill/42469/schcheck-cv-warnings-and-errors-after-updating-cdf-params/1362816#1362816"]Andrew, would it be ok to send you an email...
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RE: schCheck(cv) warnings and errors after updating CDF params
Hi Andrew, I somehow can't send you an email through here, I have sent you a friend request on here so that I can share the details with you. Please let me know if that is ok, or if there's another way...
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RE: Unable to map design without a suitable latch. [MAP-3] [synthesize]
Map design is more dependent on purpose not on media. Are you facing Qualia Collection Services Debt Collection Harassment ? Give us a shout today & get rid of phone harassment from this agency etc.
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Planar Spiral Inductor Design Process
Hello, i would like to design a planar spiral inductor on a PCB similar to the design on https://coil32.net/online-calculators/pcb-inductor-calculator.html . What is the recommended workflow for...
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RE: A GenCAM from Allegro
community.cadence.com/.../Cdc2fab.zip Hi, You might give this a try. I've had this for a long time, and believe it will give you what you want. Good day.
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RE: A GenCAM from Allegro
Also, did you try File/Export/Fabmaster Out and see if it gives you the resulting file you want? It looks very familiar.
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RE: schCheck(cv) warnings and errors after updating CDF params
I did accept the friend request, and sent a reply message that way (hopefully you got it - not sure how good the notifiers are as I virtually never use this aspect of the forums because I prefer people...
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RE: multiple gnd's passive components only system problem
I added parralel resistance to the inductor and it worked, Thanks
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Generating IBIS models in cadence virtuoso
I'm trying to generate IBIS models for the parts that I'm designing. I'm designing using CADENCE Virtuoso. I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso. Please...
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Planar Spiral Inductor Design Process
Hello, i would like to design a planar spiral inductor on a PCB similar to the design on https://coil32.net/online-calculators/pcb-inductor-calculator.html . What is the recommended workflow for...
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How to print a layout into a vector based file format (like SVG and EMF)?
Hello, I am looking for a vector-based output file format for a layout view. I was using EPS and it worked well for inserting eps into MS Word, however, MS does not support EPS insert function any more...
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vmsUpdateCellViews : How to disable/override user pop-ups?
When using vmsUpdateCellViews for the entire library on systemVerilog views, pop-ups for the HDL parser show up stopping the command from continuing. Is there a way to overcome this? Thanks, Rakesh.
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RE: How to print a layout into a vector based file format (like SVG and EMF)?
Hi Alex, Cadence tools like Schematic and Layout editors do not support SVG exports as far as I know, I just checked and there is not such option. Your best bet is to print your layout into an EPS then...
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