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RE: vmsUpdateCellViews : How to disable/override user pop-ups?
Hi Rakesh, Here are some SKILL variables you can setup in your Virtuoso session to avoid such pop-ups, you can copy theme from the following snippet link , which I also pasted below for convenience:...
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RE: geGetSelSet() not worked on softblock's shape
Andrew, Thank you for your help, it worked. Best Regards Amos
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how to plot MOS Capacitors(cgs,cgd) with respect frequency ?
hi all In RF IC DESIGN i want to know that frequency response of mosfet parasitic capacitance .
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RE: Planar Spiral Inductor Design Process
Hi maybe this can help you. It is a very good tool. http://www.saturnpcb.com/pcb_toolkit/ You may already be aware but your are talking very low inductance for these types of inductors typically in the...
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RE: Unable to map design without a suitable latch. [MAP-3] [synthesize]
All maps should have a few elements which help with understanding the depicted information: scale, legend, source, title. https://www.bestassignmenthelp.co.uk/
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Repeat option in vpwl source
Hi, When we are using vpwl voltage source in cadence test benches, we can create a particular waveform by providing voltage versus time information. Let us say, we want to repeat the same voltage...
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net assignment question
hello how can i assign a net as a ground or power? based on the artical below, i should identify the power and ground nets in order to maximize the performance but i do not know how....
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Part Number : Null
Hi I have a problem regarding the Part Number. When i login through CIP, I can find that connector and can place it on schematics. But when i use place database part option using CIS explorer, it...
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RE: Planar Spiral Inductor Design Process
Give this free app a try orcadmarketplace.com/.../Default.aspx
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RE: net assignment question
In Constraint Manager go to Properties - Net Properties - General and add a Voltage value for the Power and GND nets. They will then display differently in the design (so not point to point but show a...
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RE: schCheck(cv) warnings and errors after updating CDF params
Hi Abhi, I've reproduced the problem with the PDK reference you provided me and identified what is wrong. I've alerted our foundry team and asked then to follow it up to get this corrected. As you said...
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RE: A GenCAM from Allegro
Hi Dave I'm still around, no worries. I'm attaching the code here Use at own risk community.cadence.com/.../ns_5F00_aegis.zip best regards Ole
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RE: net assignment question
thank you steve i was able to set up the ground and power nets and saw a cross in the middle on each pin. but i do not see any significant performance difference on each command yet. you always help me...
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RE: Repeat option in vpwl source
It rather helps if you specify which simulator you're using. I'm guessing you're using the hspiceD interface and running HSPICE, because that's not what the form looks like if you have "spectre" in the...
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RE: how to plot MOS Capacitors(cgs,cgd) with respect frequency ?
This doesn't make sense. They don't vary with frequency - they are capacitances (or partial derivatives for some models) which are dependent upon the DC operating point. Of course the impedance of...
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RE: Repeat option in vpwl source
Hi Andrew, Thanks for the solution. Yes, interface was hspiceD. I have changed it to spectre by following the options you suggested. Below is the vpwl form where I can fill the period details. Thanks...
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RE: Repeat option in vpwl source
Er, didn't I explain this before? You also didn't say which simulator you're actually using. If you're using Spectre, it's in "Period of the PWL". If you're using hspiceD, then it's "Repeated Function"...
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RE: Repeat option in vpwl source
Hi Andrew, My simulator was spectre and still the period option was not appearing. In the schematic options environment was default set to hspiceD. Because of this, I was getting this problem.
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How to check the DC operating condition of a MOS in extracted netlist simulation
Dear All, There is deepprobe to find the node potential at the TestBench level while doing PEX simulation. Is there any way to check the DC operating condition of a MOS during extracted netlist...
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