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Fail to export pdf using ghostscript
Hi Im using Orcad 17.2 and the script used for exporting schematic pdf's is Ghost script gswin64c.exe. But Now i'm getting an error while exporting pdf which is, ERROR: undefined OFFENDING COMMAND:...
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Are inherited connections supported by layout XL
Hello, I have a problem with inherited connections of the schematic. I have an inverter using an inherited connection for vdd and vss. The correct netname is assigned by setting a user property. This...
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RE: skill code needed for connecting via on device to corresponding net below...
HI Andrew, Given Below images depicts my question. Suppose i have a device with via (here M1V1M2) & Netname of via is (vdd&vss). Two metals(here M3)are running parallel to device whose netnames...
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RE: Fail to export pdf using ghostscript
You haven't mentioned which exact version of OrCAD Capture (I guess) that you are using, check from Help>About, but I suspect that the schematic may be corrupted, try copying the schematic pages to...
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RE: Fail to export pdf using ghostscript
Problem solved , I dont know the exact reason but I assume it was the mistake of printer. I have changed the default printer (OrCADPS_17.2) in " Devices and Printers " to another one and gave that name...
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RE: Random numbers after net name
As oldmouldy says -- since you did not identify to Orcad that you wanted these to be connected (off-page symbol) or global (global symbol) Orcad makes them unique. You might look into using the Global...
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RE: skill code needed for connecting via on device to corresponding net below...
Raghu, This does seem to be trying to reinvent the pin to trunk capability that is already in VLS XL. Why don't you use that? You can either draw the VDD and VSS trunks and as you do so use Right...
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RE: how to copy right PART reference in multiple board design in 16.3
We only do the copper for one board but we make a panel drawing that is included for the fabricator if we need to control panelization. We never copy the copper to the other panels. Otherwise we leave...
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RE: How to specify a SPICE source file in Virtuoso hierarchy Editor (config...
Fahmy, This would need the "hdb" SKILL functions to edit a config view, but unfortunately there is no SKILL function available to set the source file attribute using SKILL. The couple of previous minor...
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RE: Display problem when I zoom in multiple waveforms
Hi Andrew, "sub-version IC6.1.7-64b.500.6 " I use ADE L to simulate the circuit and plot the waveforms. Best, Christon
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RE: Display problem when I zoom in multiple waveforms
Christon, Try using: envSetVal("viva.graph" "enableLV" 'string "false") (You may need to do this in a fresh Virtuoso session before opening VIVA). If this fixes it, please first try if it's resolved in...
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ipcBegin Single Quote Escaping
Is there a way to escape a single quote (') when using the interprocess communication ipcBegin function? I would like to provide an arguement to a program which contains a single quote (') I've tried...
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RE: How to Save Optimized Design Variables to a new Corner for Later Simulation
Hi Andrew, This works great. I like the menu addition. Thank you for your help. I need to now envision how I would want the enhancement to work from a customer support perspective. I believe that if...
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RE: Display problem when I zoom in multiple waveforms
Hi Andrew, Yes, this command fixes the problem. However, if I open Virtuoso without keying this command, the problem still exists. I tried our latest version 6.17.706 and the problem is the same. So...
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RE: ipcBegin Single Quote Escaping
Curtis > cid=ipcBeginProcess("echo \\'hello\\'") ipc:2 > ipcWait(cid) nil > ipcReadProcess(cid) "'hello'\n" Because backslash means an escape in SKILL, you need to escape the shell escape. Andrew
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RE: Display problem when I zoom in multiple waveforms
6.17.706 is the same version you mentioned earlier - it's just the release management numbering scheme - but this corresponds to 6.1.7.500.6 (ISR6) which is relatively old. Setting that environment...
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RE: Display problem when I zoom in multiple waveforms
Noted with many thanks. Best, Christon
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Integrating AMS IP in SoC Verification Just Got Easier
Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we...
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RE: Are inherited connections supported by layout XL
when you say "in layout the generic net name is assigned to the pin..." do you mean inside of the inverter layout or wires routing to that pin in the cell where the inverter is instantiated? If the...
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