RE: Inconsistent behavior of axlDBCloak?
Can you try to put a axlDBRefreshId(nil) after the via creation? I use a similar piece of code creating many vias with netnames, but never had any problem with this. The whole function is called with a...
View ArticleRE: How to Save Optimized Design Variables to a new Corner for Later Simulation
Justin, I added an option to do this - you'd pass ?addModelGroup "ModelGroup" to the function now. To make life easier, I create a form (this code requires IC617 to work) and also the ability to add...
View ArticleThe Old Order Changeth: Samsung Passes Intel
The most famous line of Tennyson's poem Morte D'Arthur is "The old order passeth, yielding place to new." It is often quoted when a new king, real or metaphorical, is crowned. Last week, Intel and...
View ArticlePromote SVA failure to uvm_error
How could the System Verilog Assertion failures be promoted to UVM_ERROR to be reported by the UVM environment? I am aware that it can be coded as: assertion_name : assert property ( // ... ) else...
View Articleskill code needed for connecting via on device to corresponding net below pcell
Hi , Suppose I know the net names of via's placed on device & corresponding nets in some metal are running below the device. Is there any function in SKILL which can be used to connect via's to...
View ArticleRE: Allegro - Stuck with red DRC status, nothing in DRC Report
Thanks mcatramb91 . That didn't solve it, however, I was able to get it fixed. By intentionally creating a DRC error, and then fixing it... Then clicking the Update DRC button. Probably just a bug.
View ArticleRE: skill code needed for connecting via on device to corresponding net below...
Hi Raghu, Not sure I understand what you mean. You add a via onto a net using dbAddFigToNet(), but if a via is already on a net, you can't add it to a second net. So perhaps you need to clarify (maybe...
View ArticleHow to rename a cell and re-reference in top level schematic
Hi I want to change my cell names and add a prefix to all of them. Then I need to re-reference my top level schematic to the new cells. One way to do this is to manually change the cell names and use...
View ArticleRE: How to rename a cell and re-reference in top level schematic
Hi, Look for the code " CCSHierCopyWithPrefixSuffix.il " on the Support site (Perhaps try this link ) You would need to copy with the rename and then later delete the originals once you've confirmed...
View ArticleCapture cloud?
Just saw this: https://orcadcloud.ema-eda.com/ema-eda Looks like a scaled down version of Capture's desktop application in the browser. The information seems scarce around this. Anyone know what...
View Articlespecifying a SPICE source file in Virtuoso hierarchy Editor (config view)...
Hi, In the virtuoso Hierarchy Editor (config file) one can right click a certain cell and choose set cell view --> Specify SPICE source file and then enters a path to a certain spice netlist file,...
View ArticleRE: How to activate "Highlight Individual Shapes" in leMarkNet( ), WITHOUT...
This works perfectly, Quek. Thanks much for saving tons of my time! -Daniel
View ArticleWhat’s the Deal with ISO 26262?
Last time I had a flat tire, I pulled my truck into one of those side-of-the-road gas stations. The attendant walks out, looks at my truck, looks at me, and I swear he said, Tire go flat? I couldn’t...
View ArticleDisplay problem when I zoom in multiple waveforms
I have some waveforms to be plotted. Before zoom in it, the waveforms look good: However, when I zoom in it, we can see that the waveforms are totally wrong because they should be straight with...
View ArticleRE: cdsMsgServer.exe - entry point not found
I was able to fix it by running the following. C:\Cadence\SPB_17.2\tools\ InstallUtils, run the InstallDiagnose.exe
View ArticleHow do you right justify multi-line labels?
I have a 2-line instance label that I've created by extracting various attributes from the cell via some skill code. I don't want to break the 2-line label up into 2 separate 1-line labels, and each...
View ArticleRE: How to import TSMC 180 nm standard I/O Library TPD018NV into Cadence
nice and interesting post 24*7 Perdisco Assignment Help
View ArticleRE: How do you right justify multi-line labels?
So while waiting for a response I did end up writing some code to make the string lengths the same by padding the smaller one with leading spaces. Sigh, now it's apparent that the font used by Virtuoso...
View ArticleMenu Assura only in windows Layout not present in the window Schematic
Hi, All. I noted that menu Assura only in windows Layout and not present in the windows Schematic. I think menu Assura should also be in the Schematic window? Or I am mistaken?
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