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RE: Sense gate metal1 in pcell(lowest hierarchy) and draw metal1 path to...
[quote userid="4936"...
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RE: Maintain "Persistence" of Find after done command is completed while...
I'd be an advocate for using cds_site if it's a multi-user environment for those that would use the same scripts or other files. You can use cds_site as well as a 'personalized' environment without...
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RE: Maintain "Persistence" of Find after done command is completed while...
When I have more UI enhancements from our users, I'll be sure to send them along to you.
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RE: Assura LVS Parameter Mismatch Error
Tony, When you say it only works when just 1 finger is used, do you mean just 1 finger in the layout? If so, then have a look at the netlist on the schematic side. Since you said it was a generated...
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RE: Assura LVS Parameter Mismatch Error
To clarify, I tend to agree with Andrew in that it is not likely Assura, but perhaps the deck, which points at the PDK and thus the foundry. That is our suspicion for our own issues as well, but at...
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RE: Function to create or edit mouse popup gui
_lxHiMousePopUp() , perhaps? Hi Paul!! (It's JimB... as of just today, finally, I'm on the forums)
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Problem in applying built-in Connect Rule
Hi. This is my first time in mixed-signal simulation. I was trying to apply connect rule. And I got this error. MESSAGE: xdlib_openPakLib: failed to seek end of bfp of library 'connectLib' I attatch...
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RE: Problem in applying built-in Connect Rule
First of all, you’re using an ancient version of the simulator - why are you using something that is probably getting on for 10 years old? There’s an article on this error on support.cadence.com -...
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RE: Multi-trace routing
"Any" PCB Editor version will support this. Routing from Pins: General Edit Application Mode, set Pins in Find, window the Pins to select, hover over a selected Pin and right-click>Add Connect, and...
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RE: Efficiency of associative array
Incisive is a legacy product and isn't being developed any more. Its replacement, Xcelium, has many enhancements and optimisations, so if you are concerned about performance, please consider upgrading...
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RE: Multi-trace routing
I checked with an OrCAD PCB Designer Standard (PCB Editor Basics) license, 16.6-2015 and 17.2-2016, latest hotfixes, and they both offer Multi Line Route for the Route>Connect command. I guess that...
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RE: Cadence 17.2 Continuous Refresh problem
File a support ticket at support.cadence.com
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Passwords: Just Add Salt
This is a second post about passwords, picking up where Passwords: How Even Your Bank Doesn't Know Your PIN left off. We left off yesterday with the problem that the bad guys can get a whole load of...
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RE: Maintain "Persistence" of Find after done command is completed while...
Paul, another document that you can look-up are the " Allegro Tips and Tricks ". These have been put together by some of the experts with the tools at Cadence and are often presented at CDN Live too....
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RE: Need help in writing Skill for routing between two different MOS
Hi Andrew, I added transforming co-ordinates function to the above code & I am able to get the result, similarly I want to append corresponding net names of each terminal to the below code, Is...
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Warning envSetval: Can't set the value of variable 'pathPurposeList', in...
Hi, I am getting a series of warnings upon initialisation of Virtuoso. All errors are in the CIW window. All of the same type as below: ""Warning envSetval: Can't set the value of variable...
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RE: #ifdef #else #endif inside module instantiation in Verilog
It looks like the person who created your Verilog example was using the C preprocessor to handle his defines and macros. Your example shows #ifdef which will work for C. The Verilog preprocessor uses...
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RE: #ifdef #else #endif inside module instantiation in Verilog
Good catch Tom, I've been writing C code all day and totally missed the # versus back-tick typo!
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