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RE: RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute
I'm having a similar issue when using nanoRoute. When I dump my technology file, the via definitions appear to be there. Additionally, when I place the design I can see that the tool is able to drop in...
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RE: RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute
The Forum Guidelines ask you not to post questions in old threads - and in this case it may be better answered elsewhere. So I'd suggest you ask the question in the Digital Implementation forum, which...
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RE: RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute
Thank you Andrew, I will repost as a new question.
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RE: Title Block strings
I am having the exact same problem. I have a title block part that I would like to modify. The original title block has fields such as the project name that gets auto-filled with the name of the...
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RE: Title Block strings
Before I answer this, let me first check which tool you're talking about (the field names don't sound like those from Virtuoso Schematic Editor, so I'm just checking what tool you are using first)....
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RE: Title Block strings
HI Andrew, you are right, I am working with Allegro HDL and, for the block titles, I am using Part Developer 17.2. I did not realize the process was different for Virtuoso. Anyway, I am finding...
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RE: Title Block strings
Hi Paolo, In which case you would be better to ask this question in the PCB Design forum, as that's where questions about the Allegro platform are likely to be answered. Regards, Andrew.
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Innovus NanoRoute Errors with LEF DEFAULT constraint group
I'm having trouble getting the nanoroute tool to route my design. I receive a slew of warnings related to the LEF DEFAULT rule. These warnings and errors are listed at the end of this post for...
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RE: Title Block strings
Hi Jacob, Since this one popped up to the top again because of the questions from Paolo below, did you take a look at Chapter 4, Creating a Multisheet Schematic , of the Virtuoso Schematic Editor L...
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How to create a title block?
Re-posting here as I initially posted my question in the wrong section of these forums. Is there any guide on how to create a title block? I have been looking on the forums and googled it but I still...
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RE: Innovus NanoRoute Errors with LEF DEFAULT constraint group
Rob, this was detected as spam because of the text repetitions in it. I took it out of moderation as it's clearly not. Hopefully somebody in this forum can help you out. Regards, Andrew.
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GTC: GlobalFoundries Pivots
Tuesday was the GlobalFoundries Technology Conference GTC. GF announced earlier in the month that they are dropping 7nm and are focusing all their effort on differentiated processes, in particular FDX...
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RE: How to create a title block?
Ok, so after a lucky find I managed to answer my own question. Posting here for future reference and to help lost souls like me... Fist of all, the key word is CUSTOM TEXT. Second of all, kudos to this...
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RE: How to create a title block?
Isn't it a shame that this only exists in the Schematic environment and not in Allegro PCB Designer.... edit text is boring..... why oh why isn't there a custom text... grr ! I did our templates...
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RE: How to create a title block?
Hi Chris, I see what you mean. I think I was once given a PCB design file with a text block but I suspect it was also edited by hand. As soon as I have a chance I will ask the engineer who designed...
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RE: How to create a title block?
Hi Chris, Using the Allegro Productivity Toolbox license option will give you access to Custom variables (Setup > Custom Variables) which will allow you to update placeholder text on the design,...
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RE: How to create a title block?
... isn't it a shame that I just locked in our Cadence licences for the next 3 years..... I wish I had known about this before.... although, I don't know the cost !. A lot of interesting features with...
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RE: Innovus NanoRoute Errors with LEF DEFAULT constraint group
UPDATE: I've found that I can successfully perform an "Early Global Route", and all of the signals are connected with the proper via definitions in the LEF DEFAULT spec. However, this does not change...
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Winning With Fewer PCBs
By John Burkhert Jr The business world keeps score with dollars and cents. The overhead cost of layout and material cost of bare boards are a significant drain on capital. Face it; Printed Circuit...
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RE: Displaying special characters in the Units column in the Assembler...
Oh well Thanks Andrew After I posted the ticked I tried axlOutputPutUnits and the three octal bytes were interpreted individually. I guess I'll make a lookup table to replace any (common) unicode...
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