Clik here to view.
RE: THD of an RF Amplifier
You can do this with pss or hb analysis. On the Results->Direct Plot->Main Form:
View ArticleClik here to view.
RE: is there any way that we can run lvs with schematic in OA virtuoso...
Well, you could do a couple of things: File->Export->CDL in both versions to produce a CDL netlist and then use your LVS tool to do a schematic-versus-schematic check File->Export->Stream...
View ArticleClik here to view.
CDNLive India: Invecas and FD-SOI
Today it is GTC, the GlobalFoundries Technology Conference. I will be there and I will cover what was said later in the week. When I was at CDNLive India a couple of weeks ago, one highly relevant...
View ArticleClik here to view.
Virtuoso - The Next Overture: Introducing Simulation Driven Routing
The new release of the Virtuoso® platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven layout for more robust and efficient design implementation...
View ArticleClik here to view.
Never Lose Your Way Again With These Nifty Maps
CDNLive India took place a few weeks ago and we are just trying to catch our breath! If you missed it, I'm going to be posting two cool videos before the weekend with the highlights. Here are two blogs...
View ArticleClik here to view.
How to simulate a PCB with PSpice
Hi folks I watched tutorial on youtube but am still very confused with PCB SI. First of all, my UI looks different. I'm using Orcad PCB SI S038 SPB. Do I need a special license to enable simulation...
View ArticleClik here to view.
Clik here to view.
RE: is there any way that we can run lvs with schematic in OA virtuoso...
Hi Andrew, When I do " File->Export->CDL" it is OK for schematic in OA virtuoso but in ICFB I got the error like " ERROR: Netlister: unable to descend into any of the views defined in the view...
View ArticleClik here to view.
Orcad Layout importing a .MAX file into footprint library
Hi, I'm working on a layout thats halfway done by a former engineer, and I cant seem to find the .LIB file or the footprints. I was thinking of making a copy of the .MAX file, renaming it, and then...
View ArticleClik here to view.
RE: skill script to add layout pin for given metal intersect
Thank you Paul and Andrew. Both code are working like charm if my metal are in top most cell of hierarchy. What if some of metals are down in hierarchy ? Can we modify script to travel through hierarchy ?
View ArticleClik here to view.
RE: skill script to add layout pin for given metal intersect
Its a little more work to go through the hierarchy to trace a net. If you dont have a trace script you might want to try the markNet functions and save the trace to a alternate view. Then you can do...
View ArticleClik here to view.
RE: verilogA simulation of 2nd order Sigma-Delta modulator
Dear VivekNITg , I know that you have posted the above question a while ago, but I was wondering if you could share your experience with me. because I have the same issue as what you mentioned above. I...
View ArticleClik here to view.
RE: skill script to add layout pin for given metal intersect
The abe functions will by default find all shapes throughout the hierarchy - there are several ways to limit this (including the ?depth argument to abeInit). If the shape with the connectivity...
View ArticleClik here to view.
RE: verilogA simulation of 2nd order Sigma-Delta modulator
Hey, I didn't have the solution to this problem I tried but couldn't get the right answer for the same. Instead, I used Ideal VCVS and other models from the analogue library and realises the...
View ArticleClik here to view.
RE: Orcad Layout importing a .MAX file into footprint library
In the Library Manager, you can use "Add" and change the "Files of Type" to .MAX to add a .MAX file as a source (or something along those lines), you can certainly have a .MAX source added to the...
View ArticleClik here to view.
RE: is there any way that we can run lvs with schematic in OA virtuoso...
Hi Nhumai, How do you perform LVS in IC5141 if you aren't able to generate a CDL netlist? What tool are you using? [quote userid="396529"...
View ArticleClik here to view.
RE: verilogA simulation of 2nd order Sigma-Delta modulator
I would suggest working with customer support on this as I stated a couple of years ago in my previous response to the original question. That would allow more detailed investigation of what is wrong...
View ArticleClik here to view.
RF Design with Cadence Virtuoso and National Instrument's Axiom
When cell-phones first became a consumer product, a VP of Nokia drew me an upside-down triangle, with radio at the top. chips in the middle, and the little point at the bottom being software. When...
View ArticleClik here to view.
RE: Cadence Allegro 17.2 - Shape to board outline clearances.
Thanks Paul, Basically yes..... I need for example NET 1 to respect a clearance of 1MM to the board each and NET 2 to respect 4MM to the board edge. I was hoping to just throw a shape at the board and...
View ArticleClik here to view.
WARN MESSAGE: (IMPESI-3014): The RC network is incomplete for
Hi, I'm running a postCTS hold fix with INNOVUS 17.15, and I've some warning message like the following: WARN: (IMPESI-3014): The RC network is incomplete for net xxx .... Do you have an idea about why...
View Article