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RE: Move or copy across layout hierarchy
The short answer is yes it can be done. We have done it and it isn't trivial. It is not easily extracted from our code for me to post since it is embedded in our custom ascend/descend code. We've had...
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RE: How to Hide Hierarchical Ports for Isolated Power Rails
It's been a while since I've tackled this problem. Here is what is in the back of my mind. It sounds like you are using POWER pins for the symbol power which will automatically revert to global if not...
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failure with using amsd block
Hi All I am trying out to use amsd block to configure some cells to be bound to a spice netlist. inside the amscf.scs file, I am writing some thing like: include "analog_top.scs" //hierarchical netlist...
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RE: failure with using amsd block
Hi Yi, tools internally create the spice-skeleton file, you shouldn't care about it. it is not clear by statement " Unfortunately, the end results is not good ", could you please explain. Thanks Nasser
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RE: Move or copy across layout hierarchy
Thanks Derek for the reply. My thought process is similar to yours. I will use custom copy or move commands. Any help here is always welcomed -Ramakrishnan
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What's For Breakfast? Video Preview September 24th to 28th 2018
https://youtu.be/NYsYkQzZADo Coming from SAP Center, San Jose (camera Sean) Monday: EDPS: Design Process in Milpitas Tuesday: CDNLive India: Invecas and FD-SOI Wednesday: RF Design with Cadence and...
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RE: Not allowing Dynamic shape on etch layer
In Color dispaly switch on all layers, I guess there is some Route keepout shape is preventing Dynamic copper to flood. or if you see the DRC when the shape was static, it will clearly tell you, "Shape...
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RE: Mark-net usage
Hello Nhumai, I guess that everything gets highlighted because the markNet Options are not correct. First of all, you need to make sure that you have defined "Stop Layers". For instance when stop...
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RE: Howto run Cadence testbench examples in ./tools/dfII/samples/artist
The sample libraries in the Virtuoso release aren't really intended to be tutorials - they are examples that have historically been used for various things now and again - some are components with...
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Calculation of microstrip impedance in topology extraction (Allegro PCB SI)
I am new to PCB SI. I have got a problem of calculated microstrip impedance in Allegro PCB SI. I could address the problem that the doubtful calculation results were the microstrips whose traces were...
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RE: QRC .rcx_setup.tpl file
This file is created by QRC automatically in Virtuoso launch directory reflecting the options you used in the QRC GUI. But if you have a template available in the PDK, then QRC will read the same when...
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Jaswinder's Only Job Interview
On Labor day, I didn't get the day off since I was in Delhi. I had to labor, not celebrate it by eating barbecue. Instead, I ate chicken curry, naan, and fried okra at the lunch I had with Jaswinder...
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RE: axlAddOutputExpr() does not plot signal
Hi Nicolas, Actually the right way of adding measurements is using axlAddOutputs() and axlOutputResult().Then the waveform icons and scalar results would be displayed in Results. Also, looking again...
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alter option
Hello, Before running my transient simulations, I want to change the multiplicity factor of some blocks. ( I am using spectre / spectreXps ) I use the command lines below. Does the simulator change the...
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RE: alter option
It will apply all the alters. Each has a unique instance name anyway and it's evaluated sequentially in the order of the alters. Andrew.
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RE: Not allowing Dynamic shape on etch layer
Without seeing the actual board, it looks like your Shape to Pin/Via values are set incorrectly (very large). So check Constraint Manager - Spacing rules for Pin to Shape etc. I'd also check the Shape...
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RE: Not allowing Dynamic shape on etch layer
Thanks All!! Steve I had the clearances set to high.
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RE: How to Hide Hierarchical Ports for Isolated Power Rails
I am not sure if your answer is addressing the particular problem I am trying to describe. Let me try again to describe a simple case: I have a hierarchical block that has two nets: AGND PGND AGND is a...
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RE: D.I.E format
I want to enable optical shrink and prefill the value when using die text-in wizard. How do you embed a die shrink in you die.txt? I know some import options like below, but I can't even find...
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Saving node voltages in Cadence
I am trying to save 'all' the net voltages inside 'some' of the blocks in my circuits. I would like to emphasize that I am not intending to save all the net voltages inside the 'entire' circuit. In...
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