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Assura DRC doesn't zoom to errors
We are using Assura 4.15. When running DRC, the errors are listed in the ELW. When we try to locate the errors in the layout, error markers are visible (barely) because it does not "Zoom to Error". It...
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What is Meltdown? How Can It Affect Both Intel and Arm?
If you pay attention to anything to do with processors, security, or even investment discussion sites covering companies like Intel, you may be aware that 2018 has started with the discovery or a major...
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Simulation of voltage doubler
I want to design a voltage doubler(Using Dickson charge pump with 2 clocks) with input voltage=Vdd=3.3V output voltage=approximately =>6 volts Frequency=1MHz capacitance=5pF I took period of clock...
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RE: Orcad Capture - Slow Graphics response on windows 10
Well in a way you have confirmed that I was not loosing my mind. I did a little more digging on this and here is what I found. I ran a windows "Proc Trace" on capture as it loads on windows 10. The...
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RE: pass ncsim commands through irun
Hello Andrew, thanks a lot for the input. Indeed it works... but unfortunately it causes an issue in the connect phases of one of the uvm agents. I haven't investigated yet since the agent is an...
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RE: Fail to run with user defined the "connect rules"
Hi Andrew My colleague helps me find the root cause. When I generate the connectRules.il by using the genConnRulesFile command, I only put the .vams file for the rule definition in the -lib argument....
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RE: Fail to run with user defined the "connect rules"
Yi, Glad it's resolved! Thanks for feeding back the solution too so that others can learn from it. Regards, Andrew.
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LAYOUT XL - auto route - route with wire assistant overrides
Hi , Scenario : I am using cadence version IC6177 , layout xl and exploring auto route option for routing between analog modules. On right clicking the net , choosing the option .. net ->route with...
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CES18 Preview
It's the start of a new year and that means it is the Consumer Electronics Show in Las Vegas. Although it is a zoo, it is a good place to get a feel for what is new in the consumer electronics space...
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SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)
Enabling Constraint-Driven Design With the pre-layout testbench built, populated with relevant models, and producing realistic simulation results, it is time to get constraints in place to drive and...
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RE: Warnings while creating the NETLIST
The length of the name "CERAMIC_ANTENNA_0_WE7488930245_WE7488930245" is 44 characters. The default setting for the name length is 31 You need to set the Long name size to > 44. If you are importing...
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Capture database linking
We recently replaced our Access database with a SQL database. We are reusing schematics that were linked to the old database. I now need to link them to the new dB because we are no longer supporting...
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RE: Capture database linking
If you are using the same database data but migrated to SQL Server, you should be able to "simply" update the Part Status in Part Manager, since it's just the Part Number that is the key that joins. If...
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Automatically Reusing an SoC Testbench in AMS IP Verification
The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification...
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RE: Capture database linking
Think I have it figured out. The problem was that we have custom names for the part number property (MFGR_PN). What I did was copy the MFGR_PN column and paste it into Part_Number. Now it will link....
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RE: Simulation of voltage doubler
Since this is a more design related question, you may be better off asking on http://www.designers-guide.org/Forum/ Andrew
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RE: pass ncsim commands through irun
If there is, I don't know how to do this (without spending some time hunting - maybe there is). Probably more of a Functional Verification question than mixed-signal. I suggest you contact customer...
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