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Androids and Electric Sheep
Deep into that darkness peering, long I stood there, wondering fearing, doubting, dreaming dreams no mortal ever dared to dream before. —Edgar Allan Poe I have a problem. As I try to go to sleep at...
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How to judge a VIP is a good VIP?
How to judge a VIP is a good VIP? And in the process of development, what we should be careful? Thank you
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Cross Section Editor impedance calculator missing in 17.2?
Good morning, we recently upgraded our license from Allegro 16.4 to 17.2 and I am familiarizing with the new UI. I cannot find the impedance calculator tool that used to be in the cross section editor....
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RE: Cross Section Editor impedance calculator missing in 17.2?
Double-click on the "Signal Integrity>>" header cell to expand and show all of the Signal Integrity parameters.
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Hierarchical design component used report
Using Concept, on a hierarchical design is it possible to generate a report that details components used per page within a block? I know PHY_PAGE will list the page number within a block but not...
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RE: Cross Section Editor impedance calculator missing in 17.2?
Duh! Thank you very much. I thought I had tried that...
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GLOBALFOUNDRIES 7nm
Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES presented their 7nm process as IEDM. See Gary Patton on GF, IBM, 7nm, EUV, and More for more details....
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RE: Orcad Capture - Slow Graphics response on windows 10
Hey guys, I too have the same problem for 2 months now and god it it is annoying. I am trying to pinpoint the problem but i cannot. I have done fresh installations, changed drivers (radeon), i even...
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Concept HDL - Hierarchical design component used report
Using Concept, on a hierarchical design is it possible to generate a report that details components used per page within a block? I know PHY_PAGE will list the page number within a block but not...
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Register for the UVM Register Layer Webinar on January 12!
On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front...
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RE: Concept HDL - Hierarchical design component used report
You could add an attribute to all of your blocks, and then that attribute would be available in the BOM tool (and/or extracta). If you have nested blocks, I think it would only give you the lowest...
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RE: Equal Spacing Spread Command
I just plop down 2 temporary vias to define the channel (with drcs, doesnt matter), spread, then delete the vias.
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RE: Nested Sweeps in ADE XL
Hi, sorry for posting on such an old thread. I was looking for exactly this and the last reply says there was something being developed. Has been any update since the time of the original post (and...
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Finding and Replacing all PCB Footprints in an Allegro/OrCAD Schematic (v17.2)
Folks, I am working with a PCB bureau that uses Allegro 17.2. I was the one that originated the design schematic in Allegro Capture 17.2. The PCB bureau uses different symbol/PCB Footprint names than I...
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VNCAP error
hi i am using virtuoso layout suite (v IC6.1.5.500.16.2). While using the vncap form technology library of 65nm CMOS; i am getting following error: " adjacent (interdigitated) Mx or By fingers must be...
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RE: Nested Sweeps in ADE XL
ADE XL has a capability called "Measurement across corners" - in the outputs setup there is a column evalType which is normally "point" for each output. You can change that to corners which means that...
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RE: VNCAP error
This is a question about the specific technology you're using - not the tool itself. Given that you didn't say which technology you're using, it's going to be difficult for anyone to answer - even...
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RE: [Help] PADS layout to Allegro PCB translation
Send me .ASC file, in format 9.3 and BASIC form, I will translate to Allegro BRD file, my email is bcasjp@centrum.cz , Jiri
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RE: PADS to ALLEGRO conversion
Send me .ASC file, in format 9.3 and BASIC form (PADSUNITS), I will translate to Allegro BRD file, my email is bcasjp@centrum.cz ,. Translation is not problém. Arcus
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RE: Need someone to convert PADS to Allegro successfully
Send me PADS .ASC file, in format 9.3 and BASIC form, I will translate to Allegro BRD file, my email is bcasjp@centrum.cz , For this, you must do - load .PCB file to PADS - make output to .ASC file in...
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