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How to retain the same impedance for a cline in both surface and inner layers
I am doing a impedance based routing, where i have set the impedance for a Cline to be 60 ohm. Once the routing is started the it routes with the line width based on the impedance given specified. If I...
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Where can I ask tools question on Synopsys VCS simulator?
I mainly used Cadence and it's the best simulator tool out there I know. But I have to do IP support to a customer using VCS. The tool is really too complex for me to get done some of the most common...
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The Birthplace of Silicon Valley: 391 South San Antonio Road
The birthplace of Silicon Valley really does have an address, 391 South San Antonio Road. In fact, it has two addresses, 844 Charleston Road as well. But the San Antonio Road one is earlier by a couple...
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RE: License Not working in user profile
Check that the user has a valid CDS_LIC_FILE environment variable set. Any user level variable will override the System level variable which might be the issue. Typically, for a multi-account machine,...
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RE: How to retain the same impedance for a cline in both surface and inner...
Assuming that you have a license level that supports Impedance rules, the width of the CLine will be adjusted to meet the impedance calculated from the cross-section materials when routing on outer and...
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RE: Skill code for getting coordinates of both ends of instances
Hi Andrew, I am trying to use the same code for finding the coordinates of all the four terminals of a mosfet(to be able to draw wire through it). But dbTransformPoint function is throwing an error...
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RE: Skill code for getting coordinates of both ends of instances
Looks like the variable "a" is a list. You'll need to take the car of the list - car(a)~>transform, or car(a~>transform)
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RE: Suppress Errors While Automatically Exporting Padstack with Shape
I want the information from the padstack. Like, padstackname and all the information from both design layers, and mask layers-- width, height, figure... If I export a padstack to xml I can get that...
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Limiting wire length while routing in innovus
Hi, I am very new to working with innovus. and I am working with a new technology (so past scripts dont work anymore) and was wondering if there is a way to force the router to limit wire lengths to...
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SDF back annotation in systemVerilog design using interfaces
I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the...
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Cannot overwrite default layout bindkey in ICADV
Hello, I am attempting to overwrite a default layout bindkey, but the desired command will not remain in the command field once entered. Using ICADV12.3 I have tried updating my bindkeys in the...
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RE: Suppress Errors While Automatically Exporting Padstack with Shape
eg: psid = axlLoadPadstack(padstackName) pad = axlDBGetPad(psid, layer, "REGULAR") pad ->??
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RE: Suppress Errors While Automatically Exporting Padstack with Shape
This link has information that does exactly what I want: https://community.cadence.com/cadence_technology_forums/f/pcb-design/24786/extracta-and-pad-files There is code in the link to export all...
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micro-via to buried via spacing
I'm having trouble getting Allegro to report a DRC for a micro-via (L1-L2) stacked over a buried via (L2-LX). It will report as a DRC until the center of the micro-via crosses the outer pads edge of...
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I have a problem adding custom vias in IC 6
Hi, I used to do this many times in IC5 and it worked fine, but our company decided to switch to IC 6 for the new projects and I am stuck. The problem is adding the customized vias that are coming with...
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RE: report_timing after clock tree synthesis shows the same clock to be ideal...
Hi Chetan, Thanks for your response. The clock propagation used to stop in the capture path after crossing initial few gates. Below settings before reporting the timing helped resolved the issue:...
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RE: report_timing after clock tree synthesis shows the same clock to be ideal...
Hello, Good to know that it is resolved now. Regards, Chetan B S
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RE: How to retain the same impedance for a cline in both surface and inner...
The issue what i am facing right now is I have a 4 layer board and a critical net is set to have impedance of 60 ohm which changes the track width to 6.31mils when routing on surface layer and when the...
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RE: How to retain the same impedance for a cline in both surface and inner...
It's not impossible that the routed width on the inner layer would be 5mils for the same impedance and only a coincidence that is also the default width. It's also unlikely that the routed width, for a...
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RE: How to retain the same impedance for a cline in both surface and inner...
Thanks And in 4 layer board the surface layer will be surrounded by air and when the track enters inner layer(layer 1) there will be two dielectric layers one above layer 1 and other below layer 1....
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