RE: report_timing after clock tree synthesis shows the same clock to be ideal on capture flop while propagated on the launch flop

Hi Chetan, Thanks for your response. The clock propagation used to stop in the capture path after crossing initial few gates. Below settings before reporting the timing helped resolved the issue: reset_clock_tree_latency * reset_clock_latency * -source reset_clock_latency -source [get_ports *] -clock [get_clocks *] reset_clock_latency -source [get_pins * -hier] -clock [get_clocks *] Thanks and Regards, Gyan