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Compromising a Fortune 500 Company...Without Hacking a Thing
Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important social engineering has become. For example, Ubiquity Networks lost $39M in 30 minutes through social engineering....
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RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Good to know. My command line skills are certainly lacking.
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RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
My auto-save is off as well, but I could try and turn it on and see if my behavior changes. I'll try that after Mike's suggestion
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RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
I tried your registry fix and the pcbenv rename together. I'll give it some time and report back.
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How to save global routing output (ie. guide for Detailed Routing)?
Hi, I want to execute global routing and export the global routing output in a file, probably a .guide file such as the ones in the benchmarks of ISPD 2018 Contest (...
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RE: Verilog A to symbol
I tried this in IC5141 yesterday (admittedly I was using MMSIM11.1 rather than MMSIM7.2 that you were using, but I doubt that makes a difference) and it works fine. I'm using subversion...
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RE: SKILL function for getting point ID (or netlist directory) in ADE XL
Hi, Try this: session=axlGetWindowSession() historyName=axlGetHistoryName( axlGetCurrentHistory(session)) rdb=axlReadHistoryResDB(historyName) foreach(test rdb->tests() printf("Point %d Corner %L...
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RE: Reversing the contents of an expanded bus in VIVA
No, you're not doing something dumb. It doesn't really know what the original signals were once the bus was created - it just outputs them in a fixed order relative to the bits in the bus. I agree, it...
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RE: how to open a .brd file in capture
ty for your reply but i want to run simulation in capture of a .brd pcb file. is it possible?
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Generating a spectre netlist(.scs) with a corner conditions in command line
I've seen answers on the support forums regarding the generation of .scs files using the command line, but I couldn't find any answers regarding the creation of spectre netlists for a corner condition....
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RE: SKILL function for getting point ID (or netlist directory) in ADE XL
Thank you for your suggestion. It looks like your code will return full list of netlist for each design points. However I think I need something slightly different. I am making a custom function that...
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Problems with simulating counter chips
hi there i'm having trouble on counter simulation. where can i find a counter library with psipce model to run? for example i want to simulate cd4060 or 74867, what should i do? many thanks
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PDF Export--> Name duplicating
Hi, I am trying to export pdf in Allegro 17.2 its getting successfully exported however file name is duplicating as shown below. Could someone please help me to solve this problem?...
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RE: Generating a spectre netlist(.scs) with a corner conditions in command line
Unfortunately your question is extremely open ended and not very precise. Are you asking about how to learn the syntax of writing spectre netlist by hand? Are you asking how to create a netlist from a...
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Packaging custom IP with block designs
Hi, I've created a custom IP block using the 'Create and Package IP -> Create a new AXI4 peripheral' flow. The peripheral works fine, so I added my own custom HDL code, and after that it still works...
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"Open IP example design" not using the requested HDL?
Hi, I'm generating some Ethernet IP on 2015.4 (10G Ethernet PCS/PMA (10GBASE-R/KR)), on two different computers. The xci requests Verilog output. On one computer, I actually get Verilog output. On the...
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IPI - Create IP from a block design
Hi, I followed along hte tutorial in UG995 (2015.2), which results in a block design as in the attached screenshot. Q: Is it possible to pack this entire block diagram into an IP block, so I can re-use...
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Knife IP and Clones Explained
Hi, When reading many forums and sites regarding gear I see a lot of misconceptions regarding trademark infringement and IP in general. I have a little knowledge on the topic so I figured I would write...
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How to write Monte Carlo file for FinFET?
I want to perform monte Carlo analysis for a FinFET inverter by using PTM-MG model, if any body can help me.
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