"Open IP example design" not using the requested HDL?

Hi, I'm generating some Ethernet IP on 2015.4 (10G Ethernet PCS/PMA (10GBASE-R/KR)), on two different computers. The xci requests Verilog output. On one computer, I actually get Verilog output. On the second computer, Vivado generates VHDL output, and modifies my xci to change the requested HDL from Verilog to VHDL. Does anyone have a fix for this? It only happens on the Vivado GUI for "Open IP example design" - running a tcl open_example_project does the right thing. For More Details: Creative video service