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RE: Allegro design entry DHL, pin swaps , export without exporting constraints, back annotate.
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RE: Sub Menus are too large
Do you happen to have two monitors at different resolutions and font scaling? If Allegro was opened on one monitor and moved to another monitor with different resolution and font scaling you may see this effect. Same would go if Allegro is running on one monitor and User Preferences opens on another. Just wondering if that is the case. I like the suggestion of running in Safe mode as window sizes and position are saved in your PCBENV folder which could cause you to move stuff from monitor to monitor. Hope this helps, Mike Catrambone![]()
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RE: Trim Silkscreen Outside Edge of Board
That works. Thank you so much!![]()
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RE: Sub Menus are too large
Hi Mike, yes, I believe that is what started the issue. I have made both monitors the same resolution but it didn't fix the problem. BUT SAFE MODE WORKED!!!!! yahoo! I've deleted the geo file and let it recreate it while in safe mode by closing the program, when I restarted everything looked perfect! Thank you very much!![]()
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RE: Question about the iprobe cell in analogLib
Hey Shawn, Thanks for the paper. The reason for my confusion were these slides (slide no.4) www.eecis.udel.edu/.../Loop Stability Analysis.pdf and also the fact that traditionally we break the loop and do small signal ac analysis by hand to find the transfer function by hand (and sometimes we use an LC network for loop gain analysis in circuit simulators). I thought that the iprobe does the same as an LC network and breaks the loop for the small signal injected into it while not loading the loop.![]()
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RE: Question about the iprobe cell in analogLib
Dear mhkvy4, [quote userid="319246" url="~/cadence_technology_forums/f/custom-ic-design/45174/question-about-the-iprobe-cell-in-analoglib/1367612"][/quote] The reason for my confusion were these slides (slide no.4) www.eecis.udel.edu/.../Loop Stability Analysis.pdf I took a quick look and see the author uses the "break the loop" terminology. Personally, my feeling is that this terminology is rather misleading. The method using an iprobe uses signal point injection and is definitely not "breaking the loop". However, if you examine the references the author includes, one is the paper I provided you. A second is the URL to Frank Weidmann's "loopgain" page at: https://sites.google.com/site/frankwiedmann/loopgain This has a lot of good information. It also contains a link to Dr. Middlebrook's video on his General Feedback Theorem at URL: https://www.youtube.com/playlist?list=PLFEq0We5q1LKsl-45zVt2A6Os__maQ2Cr [quote userid="319246" url="~/cadence_technology_forums/f/custom-ic-design/45174/question-about-the-iprobe-cell-in-analoglib/1367612"]also the fact that traditionally we break the loop and do small signal ac analysis by hand to find the transfer function by hand (and sometimes we use an LC network for loop gain analysis in circuit simulators). I thought that the iprobe does the same as an LC network and breaks the loop for the small signal injected into it while not loading the loop[/quote] If you are using large L or C values in this approach, my concern is that this will stress the dynamic range of your simulator. I have definitely had accuracy issues when using very large L or C values to "block" DC or AC signals and would be leary of its use in estimating loop gain - my personal thought only! Shawn![]()
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RE: Stimulus File Issues
There's a few issues here. First of all, stimulus files are not directly included into the simulator - they go through a process of mapping schematic names to simulator names (mostly this was useful in the days of flat netlisters when there was no clear relationship between the name on the schematic and the name in the netlist). That's achieved by using [#...] to map nets or [$...] to map instance names. For more info on this search in cdnshelp (which you can launch via the help menus in Virtuoso) for "stimulus file" or "Template Control File" (include the quotation marks in the second) to find the section which describes the syntax. In your case you've escaped the open square parenthesis, which means that the name translation doesn't happen, and the simulator gets the the literal square brackets - ([#LIGHT ] 0) - which is invalid spectre syntax. That's not what you wanted. So (in theory) you should have just omitted the backslash, but unfortunately there's a bug (CCR 752498 - has been there for some time) where the default mapping mechanism doesn't take into the account that it needs to add backslashes before the in the resulting name, so it still fails, but in a different way. The older mapping mechanism that was used in the distance past worked OK, but since it was changed many years ago, it's been broken. The fact that it hasn't been fixed yet is an indication that not many people rely on this mapping mechanism. It is possible to tell ADE to revert to the older name mapping in the netlist, but I wouldn't recommend that in general just to fix this issue. By the way, you can click on the hyperlinks in the spectre log file and see the mapped file - you will see that it doesn't directly include your file, but instead includes a copy which has been copied into the netlist directory after mapping has been performed. So, the solution is just to use the names that are in the netlist - and then you can either specify the stimulus via the stimulus file or a model library or definition file (since you don't need it to do any mapping any more, you can also use model library or definition file). If you use model library or definition file to include it, it's a bit simpler: simulator lang=spectre LIGHT1 (LIGHT\ 0) vsource dc=0.882353n LIGHT2 (LIGHT\ 0) vsource dc=1.217647n LIGHT3 (LIGHT\ 0) vsource dc=1.105882n LIGHT4 (LIGHT\ 0) vsource dc=0.988235n LIGHT5 (LIGHT\ 0) vsource dc=0.205882n LIGHT6 (LIGHT\ 0) vsource dc=0.270588n LIGHT7 (LIGHT\ 0) vsource dc=0.276471n LIGHT8 (LIGHT\ 0) vsource dc=0.258824n If you use stimulus file still, you have to escape the escape, because the mapping process removes the first backslashes: simulator lang=spectre LIGHT1 (LIGHT\\ 0) vsource dc=0.882353n LIGHT2 (LIGHT\\ 0) vsource dc=1.217647n LIGHT3 (LIGHT\\ 0) vsource dc=1.105882n LIGHT4 (LIGHT\\ 0) vsource dc=0.988235n LIGHT5 (LIGHT\\ 0) vsource dc=0.205882n LIGHT6 (LIGHT\\ 0) vsource dc=0.270588n LIGHT7 (LIGHT\\ 0) vsource dc=0.276471n LIGHT8 (LIGHT\\ 0) vsource dc=0.258824n If you want to get the real mapping issue fixed, I suggest you contact customer support and ask for a duplicate of CCR 752498 to be filed on your behalf. Regards, Andrew.![]()
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RE: Question about the iprobe cell in analogLib
Shawn, I agree, the terminology is misleading at best - the fact that it says that it is a short in DC and opens the loop for stb analysis is really just plain wrong. That's what the spt1switch (and spt[2-4]switch) components in analogLib do in an AC analysis - they allow you to have a switch which is ideally closed or open in different analyses, and was the old-school way of doing stability prior to the introduction of stb analysis. The switch approach was better than a large L/C because the large components introduced actual components which could impact the AC response, plus potentially introducing numerical errors as you mentioned. The main issue however with any of the old "opening the loop" approaches was that the messed up the loading of the loop at the point it was broken, so the results were of dubious value unless you took a lot of care to try to replicate the missing loading - and even then it still was likely to mess up the loop. So as you've said, the whole point is to keep the loop closed and directly measure the loop gain. The presentation shared by mhkvy4 is also fairly old and suggests using cmdmprobe for differential loops - although it does mention diffstbprobe as a newer mechanism. Anyone reading that presentation should not use cmdmprobe any more - it's obsolete - and diffstbprobe should definitely be used instead as it's a superior way of dealing with measuring common-mode and differential-mode stability (it uses ideal baluns to convert the differential signals into a differential-mode and common-mode path with an iprobe in each, and then back again to differential signals; the analysis then picks the specific iprobe depending on whether you're analysing the differential-mode or common-mode stability). Regards, Andrew.![]()
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RE: Main Transistors from technology file are missing after QRC Extraction
It's probably more important to try with a newer Quantus version (either EXT19.1 or QUANTUS20.1 - the release stream name changed between 19.1 and 20.1). I suspect the IC version is not so important here. You're using an older version and maybe there's an issue. It's very hard to diagnose without seeing the data, so I would suggest you continue trying via your university support route, if using the later versions doesn't fix it. Andrew.![]()
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RE: AMS simulation test failed
This is suggesting some uncaught low-level error - usually that error would just indicate that something in the code has failed to read a string from somewhere but didn't check that and then failed when it tried to process the string. Hard to diagnose... So, some things that may help narrow it down: Which IC version and simulator version are you using? Help->About in the CIW will tell you this (the simulator version can be found by typing "irun -version" in the terminal window) Which netlister are you using under Simulation->Netlist and Run Options in ADE? Is it Cellview-based, OSS or Unified Netlister? Can you type _stacktrace=50 (yes, with an underscore) and try to reproduce the problem? You should get a longer stack trace and if so, please post it here. Andrew.![]()
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RE: PSpice Student Version?
Hello students, this is a server error and mostly peoples are facing these types of problems. I hope It will be solved very soon. Day by unique technologies is developing in the markets so this is why it is affecting the server. Students should wait for some time or hire the uk academic website who offer the uk assignment writing help . They can get the best assistance and get the best information about the new version.![]()
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RE: How to add PSpice model to CIS component?
I'd be willing to spend up to around $150. This software is damn near impossible to pirate (have to set up a local licensing server, etc) as I'm sure many of you have found. I've used tools like multisim and LTSpice but none of these have the CIS option like OrCad which makes doing simulations nox acmarket![]()
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RE: axlSelect() does not select 'fillet'
Hi，i have a similiar question When I use below 3 lines, and try to select fillet at 16.6. there is no item in Cline_List variable.. Can you help me, Thank you. axlSetFindFilter(?enabled '(noall clines clinesegs") ?onButtons '(noall clines clinesegs")) axlSelect(?prompt "Select Clines.") Cline_List=axlGetSelSet()![]()
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axlSelect() does not select 'fillet' , When selecting Cline
Hi all，i have a similiar question When I use these 3 lines bellow, and try to select fillet at 16.6. there is no item in Cline_List variable.. Can you help me, Thanks All axlSetFindFilter(?enabled '(noall clines clinesegs") ?onButtons '(noall clines clinesegs")) axlSelect(?prompt "Select Clines.") Cline_List=axlGetSelSet()![]()
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RE: AMS simulation test failed
Hi, Mr. Beckett Thanks for help firstly, I checked those things you suggested. Please see answer blow. So, some things that may help narrow it down: Which IC version and simulator version are you using? Help->About in the CIW will tell you this (the simulator version can be found by typing "irun -version" in the terminal window. The IC Version is IC6.1.7 - 64b.500.18 and the simulator version irun(64) 15.20-s030. Which netlister are you using under Simulation->Netlist and Run Options in ADE? Is it Cellview-based, OSS or Unified Netlister? The netlister I used under simulation is AMS Unified Netlister with irun which is recommended. Can you type _stacktrace=50 (yes, with an underscore) and try to reproduce the problem? You should get a longer stack trace and if so, please post it here. Best Regards, Ciao.![]()
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RE: AMS simulation test failed
Hi, Mr.Beckett It works after I change NETLIST AND RUN MODE from AMS Unified Netlister with irun to OSS-based netlister with irun. I am confused why this happens because, from the features comparison, it looks that AMS UNL is a advanced OSSN. Which means, if it works in OSSN mode, it should be work in AMS UNL. Best, Ciao.![]()
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RE: AMS simulation test failed
What do you get if you type: which dna_assembler and which irun in the UNIX terminal? I checked and in that specific IC subversion, it will fail with the error you showed because it doesn't properly check that dna_assembler is in the path. In the very next hot fix (IC617 ISR19) there's an additional check which would mean it fails more gracefully - but you'd still need to have dna_assembler in the UNIX path. The first which ought to show something like: /tools/bin/dna_assembler UNL is definitely a superior solution, and using that is best - but it requires some additional executables in the path that weren't needed for UNL. Why they are not in the path (if this is the issue) is what we need to determine (my guess is that in your environment you have a wrapper around irun, but not one around dna_assembler). Andrew.![]()
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How to add solder mask to teardrops ?
Hey guys , when i was making a keyboard pcb , i found this images. this is a pcb of keyboard too . what interested me is that all of it's clines , thr-pins , vias and teardrops are added solder masks , and shows out an open-windowed , blackgold effect , and i think i want this visual effects too . then i tried it in allegro . first i export a sub_drawing file out of the pcb , selecting the clines and vias before picking the origin spot , and a .clp file is there in the folder where the pcb .brd file is . Then i open the clp file with the vscode , and replaced all of the "etch/top" and "etch/bottom" with ''Board_geometry/soldermask_top'' and ''Board_geometry/soldermask_bottom '' . then , i import the modified clp file into the pcb , and this help to add a mask layer to the clines and vias . in the 3d viewer it is like this it shows the same effect in the first image i posed , the clines , vias are added soldermask . but i can not achieved the effect in the second image , cause i don't know how to add soldermask to the teardrops . when i exported the subdrawing file , i can only select the clines vias pins but not the teardrop . Anybody knows know to add soldermask to the teardrops can give me some ideas ?![]()
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RE: How to add solder mask to teardrops ?
Anybody knows how to add soldermask to the teardrops can give me some ideas ?![]()
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How do we extract a full path design from Scoreboard when there is a `uvm_error?
Hi, How do we extract a full path design from Scoreboard when there is a `uvm_error? For example, my_module has the following assigments: (array of virtual interfaces, while each VF accepts data and data enable signals, with unique names) assign my_module_internal_vif[#num].data_en = main_tb. assign my_module_internal_vif[#num].data = main_tb. ; While there is a `uvm_error which happens in Scoreboard, I have the trans object (which is sent from the monitor). The trans has a field with instance number, but it doesn't monitor the signals themselves. I have the #num or thre error. My objective to to extract with a kind way, the full path design as a string and print it, given the number of the instance, i.e, when there is a `uvm_error, from trans[#num ], recognize my_module_internal_vif[#num] and then print the full path design which indicates which data enable was triggered and which data was compared. Thanks for your help!![]()
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