I am using cadence virtuoso 6.1.8. I have a question about the iprobe cell in analogLib. I know that it appears as a short to DC signals and as an open to small-signals during STB analysis and also acts as the signal source during STB. So it is great for loop gain analysis where breaking the loop might load the circuit. My question is, does iprobe appear as a short in XF, AC and noise analysis? Having run some simulations it appears to be the case.

Dear mhkvy4, [quote userid="319246" url="~/cadence_technology_forums/f/custom-ic-design/45174/question-about-the-iprobe-cell-in-analoglib"]My question is, does iprobe appear as a short in XF, AC and noise analysis? Having run some simulations it appears to be the case.[/quote] To my knowledge, the iprobe analogLib element does exactly what it is intended to provide. It is an ideal current monitor that does not "break" any connection in your circuit, but rather inserts an ideal zero-ohm resistor in the circuit branch under study to monitor the current through the branch. Hence, it will be a short circuit in not only the XF, AC, and noise analyses, but in all analyses. However, with respect to your comment "...and as an open to small-signals during STB analysis...", I don't think that is totally accurate. If it were to be an "open", it would disturb the loading present in normal operation. This will impact the loop gain and hence impact the analysis results. The probe simply serves to alowl a Middlebrook like analysis to be performed in order to assess loop gain and phase. Does this help mhky4? Shawn

Hello Shawn, Thanks for the prompt reply. I was under the impression that the iprobe acts as a short for DC but breaks the loop during STB analysis (similar to how we can use a LC network to inject a small signal source while preserving DC feedback). For loop gain, I thought the signal has to traverse the entirely of the loop after the loop has been broken. I am not familiar with Middlebrook and I should probably read up on it, but shouldn't the signal injected into the loop by iprobe from one of its terminals flow around it and then come out the other end into the other terminal to calculate it?

Dear mhky4. ... [quote userid="319246" url="~/cadence_technology_forums/f/custom-ic-design/45174/question-about-the-iprobe-cell-in-analoglib/1367590"] I was under the impression that the iprobe acts as a short for DC but breaks the loop during STB analysis (similar to how we can use a LC network to inject a small signal source while preserving DC feedback).[/quote] Suppose, as an example, the current probe is placed between the output node and the input node of an non-ideal amplifier with finite gain and finite input and output impedances. If the current probe were to be an "open" during the STB analysis, it would change the load impedance of the output of the amplifier as the finite input impedance of the amplifier would no longer be seen by the output node. Hence, the loop gain will not reflect the loop gain when the loop was closed. Hence, the view that the probe " breaks the loop during STB analysis" really is not totally accurate. Does this make any more sense mhky4? [quote userid="319246" url="~/cadence_technology_forums/f/custom-ic-design/45174/question-about-the-iprobe-cell-in-analoglib/1367590"] I am not familiar with Middlebrook and I should probably read up on it, but shouldn't the signal injected into the loop by iprobe from one of its terminals flow around it and then come out the other end into the other terminal to calculate it?[/quote] I was fortunate to have Dr. Middlebrook (and his student Dr, Cuk) as professors - hence I am pretty familiar with his work. His work served as the basis for the stability analysis provided by Spectre. I have some of his original papers, but think the most appropriate reference to provide you with was a more recent article authored by Michael Tian, V. Visvanathan, Jeffrey Hantgan, and Kenneth Kundert from an IEEE 2001 CAS magazine. This summary tutorial article describes the basics of Middlebrook's concept (null double signal injection) and its implementation. The paper also cites Middlebrook's original paper from 1975. I hope this helps your understanding a bit...let us know. Shawn community.cadence.com/.../00900125_5F00_striving_5F00_for_5F00_small_5F00_signal_5F00_stability_5F00_circuits_5F00_devices_5F00_2001.pdf

Hi All, I am using ICADv18.1 ISR10. I would like to autoFill some fileds in the form. Here is the screenshot: From CIW window, I could see the form name as cteForm648. I could use cteFor648->?->? to set a value. But the form name changes everytime I re-open it. I would like to know, if there is any way to get the name/details of the form that is currently open. For example, we have geGetEditCellView() to get the cellview being edited. I would like to know if similar command exists to get the details of the current form. Once I get the form name, I could use it to set the fields automatically. It is the customer code, which opens the form. So I can't ask them to put default values into the form. Thanks in advance, Baig

Hello I am using Oracd capture CIS from longtime and it was working fine till 16.x version.In 17.2 onward I am unable to view footprints on capture CIS window I explained my problem in the below image, If anyone come across the same issue and got resolved ,please help me . I did detail check on the flow cad PDF ( https://www.flowcad.de/AN/FlowCAD_AN_Capture_CIS_Environment.pdf) for the right setting but unable to figure it out the actual issue ? Regards, Girish Kumar

Hello, After running a DC simulation and want to view DC operating point, I go to ADE XL result pane and do print > DC Operating point > and click on the transistors I am interested in. But The view lists parameters horizontally which is hard to view. Every time I have to go to the expression tab and display options window and change the window so that it can display the parameters vertically. How can tell the system to display the results listed vertically? I am using: IC6.1.8-64b.500.9 and spectre191. Thank you so much in advance.

Hello Is there any way to trim the silkscreen outside the edge of the outline? I am using the SILKSCREEN_TOP subclass. Thank you.

Hi, I am trying to place and rout a simple test design using Innovus foundation flow. But at the end of the flow, I get a short between nets and cell blockage. I tried to increase the designed area to a huge value (1mm x 1mm) but the short remains. The design density is at 43%. You can see en example of short in this picture. The short is on M1. Thank you in advance for your time.

And I'm a long time user and I've never seen it either...

To give an example here is a snip of what I get when opening a sub menu, in this case the "user preferences" menu. As you can see the bottom half of the menu is off of the screen and the "OK" button and lower selections are not accessible and there is no way to scroll down. You can also see that the screen in the background is the correct size. The sub-Menu is about 4x the size it should be. .

Hi. Some questions - 1) Have you reported this to Cadence Support? 2) What Hotfix are you on? 3) Windoz 7 or 10? Again, I've never seen this display issue in all the years I've been on Allegro.

Delete/Cut (element: line)

Also the vias showing 1, 4, 7, etc. imply these are 'electrical pins'. Hence you'll need to show these in the schematic. If that's what you intend, fine. But if you only want GND vias, per se, delete the pin numbers and manage the electrical connectivity in Allegro layout.

Andrew, Thanks for all of your supports. I contacted the foundry (XFAB), they can easily run my test bench and extract the parasitics. They suggested me a couple of things, I considered them but It is not fixed yet. Last option was installing the PDK based on the latest updated versions. Not only it did not fix, but also QRC even does not run and it fails this time. Here is the error that shows that the reference node seems is not correct, but it is exaclty what I have on my schematic. Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version 17.1.2-s041 Wed Aug 23 16:57:50 PDT 2017 ------------------------------------------------------------------------------------------------------------------- Copyright 2017 Cadence Design Systems, Inc. INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not specified, it is automatically set to the input directory. INFO (LBRCXU-108): Starting /ECEnet/Apps1/linux/cad12/tools//cadence/ASSURA41_6x/tools.lnx86/assura/bin/rcxToDfII /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/__qrc.rcx_cmd -t -f /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/extview.tmp -w /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 26, errno 9 Bad file descriptor Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.03s. @(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12 01/31/2018 23:40 (sjfnl846) $ sub-version 4.1_USR5_HF14, integ signature 2018-01-31-2027 run on amml.ece.neu.edu from /ECEnet/Apps1/linux/cad12/tools/cadence/ASSURA41_6x/tools.lnx86/assura/bin/64bit/rcxToDfII on Fri May 29 12:40:26 2020 Loading tech rule set file : /ECEnet/home/student/mehdina94rm/XFAB_XT018/.assuraSetup/Assura/techRuleSets ** Info: PDK loadpath is "./.xkit/setup/xt018/cadence/PDK" Loading XfMenuXt018.cxt Loading XfSktTools.cxt Loading XfTechXt018.cxt Loading XfPcellCore.cxt function ansiSpicePrintProperties_subcircuit redefined ** Info: PDK loadpath is "./.xkit/setup/xt018/cadence/PDK" Loading XfSkillExt.cxt nil Initializing library. Finished Initializing Library . Generic PcellKit: 'production' loaded. Generic Pcell Skill Tools: 'production' loaded. INFO (LBRCXU-114): Finished /ECEnet/Apps1/linux/cad12/tools//cadence/ASSURA41_6x/tools.lnx86/assura/bin/rcxToDfII INFO (LBRCXM-642): Constructing the RCX run script Forking: /ECEnet/Apps1/linux/cad12/tools/cadence/EXT171/tools.lnx86/extraction/bin/64bit//capgen -techdir /ECEnet/home/student/mehdina94rm/XFAB_XT018/xt018/cadence/v10_0/QRC_assura/v10_0_1/XT018_1242/QRC-Typ -lvs /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC.xcn -p2lvs /ECEnet/home/student/mehdina94rm/XFAB_XT018/xt018/cadence/v10_0/QRC_assura/v10_0_1/XT018_1242/QRC-Typ/qrcTechFile -sd -reseqn -sw3d -length_units meters -cap_unit 1 -p POLY1,gate,active -M p_cap -genericMos pe_5,D,G,S:AS=AS,AD=AD,PS=PS,PD=PD,NRD=nrd,NRS=nrs -genericMos pel_5,D,G,S:AS=AS,AD=AD,PS=PS,PD=PD,NRD=nrd,NRS=nrs -genericMos pesvt_5,D,G,S:AS=AS,AD=AD,PS=PS,PD=PD,NRD=nrd,NRS=nrs -genericMos pem_5,D,G,S:AS=AS,AD=AD,PS=PS,PD=PD,NRD=nrd,NRS=nrs -dsub nwtrm,nwtrm_scr,nbase,bulk -blocking cmmh,MET4,METTPL -blocking cmm23f,MET2,MET3 -blocking cmmh23f,MET2,MET3 -blocking cmm34f,MET3,MET4 -blocking cmmh34f,MET3,MET4 -blocking cdmm,MET2,MET3,MET4 -blocking cdmmh,MET2,MET3,MET4 -blocking d_csf2p,POLY1,MET1,MET2 -blocking d_csf3p,POLY1,MET1,MET2,MET3 -blocking d_capsw3,POLY1,MET1,MET2,MET3 -blocking d_csf3,MET1,MET2,MET3 -blocking d_csf3a,MET1,MET2,MET3 -blocking d_capsw4,POLY1,MET1,MET2,MET3,MET4 -blocking d_csf4,MET1,MET2,MET3,MET4 -blocking d_csf4a,MET1,MET2,MET3,MET4 -blocking d_cif3,MET1,MET2,MET3 -blocking d_cif4,MET1,MET2,MET3,MET4 -blocking phsj1_7:0.01,POLY1,active,sub,MET1 -blocking phsj1_10:0.01,POLY1,active,sub,MET1 -blocking phsj1_16c:0.01,POLY1,active,sub,MET1 -blocking phv1_d:0.01,POLY1,active,sub,MET1 -blocking nhsj1_7:0.01,POLY1,active,sub,MET1 -blocking nhsj1_10:0.01,POLY1,active,sub,MET1 -blocking nhsj1_16c:0.01,POLY1,active,sub,MET1 -blocking nhv1_d:0.01,POLY1,active,sub,MET1 -blocking nisj1_16:0.01,POLY1,active,sub,MET1 -blocking nisj_d:0.01,POLY1,active,sub,MET1 -blocking phvta:0.01,POLY1,active,sub,MET1 -blocking phvtb:0.01,POLY1,active,sub,MET1 -blocking phvu:0.01,POLY1,active,sub,MET1 -blocking pdftrm:0.01,POLY1,active,sub,MET1 -blocking nhvta:0.01,POLY1,active,sub,MET1 -blocking nhvtaa:0.01,POLY1,active,sub,MET1 -blocking nhvtb:0.01,POLY1,active,sub,MET1 -blocking nhvu:0.01,POLY1,active,sub,MET1 -blocking ndhvt:0.01,POLY1,active,sub,MET1 -blocking ndhvta:0.01,POLY1,active,sub,MET1 -blocking ndhvtaa:0.01,POLY1,active,sub,MET1 -blocking ndftrm:0.01,POLY1,active,sub,MET1 -blocking mosvc:0.01,POLY1,active,sub -blocking mosvcm:0.01,POLY1,active,sub -blocking mosvci:0.01,POLY1,active,sub -blocking mosvcim:0.01,POLY1,active,sub -blocking pmva:0.5,POLY1,active,sub -blocking pmvb:0.5,POLY1,active,sub -blocking pmvc:0.5,POLY1,active,sub -blocking pmvd:0.5,POLY1,active,sub -blocking pmve:0.5,POLY1,active,sub -blocking pmvf:0.5,POLY1,active,sub -blocking nmva:0.5,POLY1,active,sub -blocking nmvb:0.5,POLY1,active,sub -blocking nmvc:0.5,POLY1,active,sub -blocking nmvd:0.5,POLY1,active,sub -blocking nmve:0.5,POLY1,active,sub -blocking nmvf:0.5,POLY1,active,sub -blocking ndmvd:0.5,POLY1,active,sub -blocking ndmvf:0.5,POLY1,active,sub -blocking nhvra:0.5,POLY1,active,sub -blocking nhvrb:0.5,POLY1,active,sub -blocking nhvrc:0.5,POLY1,active,sub -blocking nhvrd:0.5,POLY1,active,sub -blocking nhvre:0.5,POLY1,active,sub -blocking nhvrf:0.5,POLY1,active,sub -blocking ndhvrd:0.5,POLY1,active,sub -blocking ndhvrf:0.5,POLY1,active,sub -blocking phvra:0.5,POLY1,active,sub -blocking phvrb:0.5,POLY1,active,sub -blocking phvrc:0.5,POLY1,active,sub -blocking phvrd:0.5,POLY1,active,sub -blocking phvre:0.5,POLY1,active,sub -blocking phvrf:0.5,POLY1,active,sub -blocking dfntrm:0.5,POLY1,active,sub -blocking dfptrm1:0.5,POLY1,active,sub -blocking pdfmvtrm:0.01,POLY1,active,sub -blocking ndfmvtrm:0.01,POLY1,active,sub -blocking pem_totpE:0.01,POLY1,active,sub -blocking pem_totpP:0.01,POLY1,active,sub -blocking pmvam:0.5,POLY1,active,sub -blocking pem_ee3E:0.01,POLY1,active,sub -blocking pem_ee3P:0.01,POLY1,active,sub -split_hv_mos nmva_Device_7,,50,5,mtot:nwtrm,nsd:contSD -split_hv_mos pmva_Device_8,,50,5,mtot:bulk,psd:contSD -split_hv_mos phsj1_7_Device_9,,50,5,mtot:phv1_d,phv1_d_psd,psd:contSD,contSD2 -split_hv_mos phsj1_10_INFO (LBMISC-215205): *** Cadence Quantus QRC Extraction Techgen -trans VERSION 17.1.2 Linux 64 bit - (Wed Aug 23 16:57:50 PDT 2017) *** INFO (CAPGEN-41199): Techgen -trans results will be written to directory: /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC WARNING (CAPGEN-41613): layer 'nmva_Device_7' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmva_Device_8' not defined in LVS file WARNING (CAPGEN-41613): layer 'phsj1_7_Device_9' not defined in LVS file WARNING (CAPGEN-41613): layer 'phsj1_10_Device_10' not defined in LVS file WARNING (CAPGEN-41613): layer 'phsj1_16c_Device_11' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvta_Device_12' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvtaa_Device_13' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvtb_Device_14' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvu_Device_15' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndhvt_Device_16' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndhvta_Device_17' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndhvtaa_Device_18' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvta_Device_19' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvtb_Device_20' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvu_Device_21' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhsj1_7_Device_22' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhsj1_10_Device_23' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhsj1_16c_Device_24' not defined in LVS file WARNING (CAPGEN-41613): layer 'nisj1_16_Device_25' not defined in LVS file WARNING (CAPGEN-41613): layer 'nmvb_Device_26' not defined in LVS file WARNING (CAPGEN-41613): layer 'nmvc_Device_27' not defined in LVS file WARNING (CAPGEN-41613): layer 'nmvd_Device_28' not defined in LVS file WARNING (CAPGEN-41613): layer 'nmve_Device_29' not defined in LVS file WARNING (CAPGEN-41613): layer 'nmvf_Device_30' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndmvd_Device_31' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndmvf_Device_32' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmvb_Device_33' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmvc_Device_34' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmvd_Device_35' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmve_Device_36' not defined in LVS file WARNING (CAPGEN-41613): layer 'pmvf_Device_37' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvra_Device_38' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvrb_Device_39' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvrc_Device_40' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvrd_Device_41' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvre_Device_42' not defined in LVS file WARNING (CAPGEN-41613): layer 'nhvrf_Device_43' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndhvrd_Device_44' not defined in LVS file WARNING (CAPGEN-41613): layer 'ndhvrf_Device_45' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvra_Device_46' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvrb_Device_47' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvrc_Device_48' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvrd_Device_49' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvre_Device_50' not defined in LVS file WARNING (CAPGEN-41613): layer 'phvrf_Device_51' not defined in LVS file INFO (CAPGEN-41737): Lvs layers capswm1 capswm2 capswm3 capswm4 capswp1 cm23f cm34f cmh cmh23f cmh34f cont d_dsdf dfptrm dfwdn2_bulk dhw2_stamp dhw2a_stamp dhw3_stamp dhw_nbur gate_T?18558 gate_T?18564 gate_T?18570 gate_T?18576 gate_T?18582 gate_T?18587 hwafer1 hwntub hwptub m1_v100 m1_v200 m1_v25 m1_v60 m1_vm100 m1_vm200 m1_vm25 m1_vm60 m2_dmm m2_dmmh m2_v100 m2_v200 m2_v25 m2_v60 m2_vm100 m2_vm200 m2_vm25 m2_vm60 m3_dmm m3_dmmh m3_v100 m3_v200 m3_v25 m3_v60 m3_vm100 m3_vm200 m3_vm25 m3_vm60 m4_dm1 m4_dmh1 m4_dmm m4_dmmh m4_v100 m4_v200 m4_v25 m4_v60 m4_vm100 m4_vm200 m4_vm25 m4_vm60 met1 met1trm_dg met2 met2trm_dg met3 met3trm_dg met4 met4trm_dg mtl_v100 mtl_v200 mtl_v25 mtl_v60 mtl_vm100 mtl_vm200 mtl_vm25 mtl_vm60 mtpl mtpltrm_dg ndf_nsd ndiff nhv1_d_nsd nisj_d_psd ntapc nwtrm1 nwtrmmv p1_v100 p1_v200 p1_v25 p1_v60 p1_vm100 p1_vm200 p1_vm25 p1_vm60 pad_b pdf_psd pdfntrm pdiff pfox phv1_d_psd poly polytrm_dg ptapc pw4trm sd subblk1 tiedtub_nbuf v100_met1 v100_met2 v100_met3 v100_met4 v100_p1 v200_met1 v200_met2 v200_met3 v200_met4 v200_p1 v25_met1 v25_met2 v25_met3 v25_met4 v25_p1 v60_met1 v60_met2 v60_met3 v60_met4 v60_p1 via1 via2CON via3CON vm100_met1 vm100_met2 vm100_met3 vm100_met4 vm100_p1 vm200_met1 vm200_met2 vm200_met3 vm200_met4 vm200_p1 vm25_met1 vm25_met2 vm25_met3 vm25_met4 vm25_p1 vm60_met1 vm60_met2 vm60_met3 vm60_met4 vm60_p1 vtpl are not mapped in layer_setup file WARNING (RCXSPIC-27116): There are no non-empty MOS/LDD devices with diffusion layer 'active' and poly layer 'POLY1'. Cannot perform gate capacitance blocking for user-specified layer 'gate'. rcxspice took 0.27 user, 0.39 sys, 1.00 elapsed, 4652.0 kbytes Device_10,,50,5,mtot:phv1_d,phv1_d_psd,psd:contSD,contSD2 -split_hv_mos phsj1_16c_Device_11,,50,5,mtot:phv1_d,phv1_d_psd,psd:contSD,contSD2 -split_hv_mos nhvta_Device_12,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos nhvtaa_Device_13,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos nhvtb_Device_14,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos nhvu_Device_15,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos ndhvt_Device_16,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos ndhvta_Device_17,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos ndhvtaa_Device_18,,50,5,mtot:ndftrm,ndf_nsd,nsd:contSD,contSD1 -split_hv_mos phvta_Device_19,,50,5,mtot:pdftrm,pdf_psd,psd:contSD,contSD1 -split_hv_mos phvtb_Device_20,,50,5,mtot:pdftrm,pdf_psd,psd:contSD,contSD1 -split_hv_mos phvu_Device_21,,50,5,mtot:pdftrm,pdf_psd,psd:contSD,contSD1 -split_hv_mos nhsj1_7_Device_22,,50,5,mtot:nhv1_d,nhv1_d_nsd,nsd:contSD,contSD2 -split_hv_mos nhsj1_10_Device_23,,50,5,mtot:nhv1_d,nhv1_d_nsd,nsd:contSD,contSD2 -split_hv_mos nhsj1_16c_Device_24,,50,5,mtot:nhv1_d,nhv1_d_nsd,nsd:contSD,contSD2 -split_hv_mos nisj1_16_Device_25,,50,5,mtot:nisj_d,nisj_d_psd,psd,nsd:contSD,contSD2 -split_hv_mos nmvb_Device_26,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos nmvc_Device_27,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos nmvd_Device_28,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos nmve_Device_29,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos nmvf_Device_30,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos ndmvd_Device_31,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos ndmvf_Device_32,,50,5,mtot:ndfmvtrm,nsd:contSD -split_hv_mos pmvb_Device_33,,50,5,mtot:pdfmvtrm,psd:contSD -split_hv_mos pmvc_Device_34,,50,5,mtot:pdfmvtrm,psd:contSD -split_hv_mos pmvd_Device_35,,50,5,mtot:pdfmvtrm,psd:contSD -split_hv_mos pmve_Device_36,,50,5,mtot:pdfmvtrm,psd:contSD -split_hv_mos pmvf_Device_37,,50,5,mtot:pdfmvtrm,psd:contSD -split_hv_mos nhvra_Device_38,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos nhvrb_Device_39,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos nhvrc_Device_40,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos nhvrd_Device_41,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos nhvre_Device_42,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos nhvrf_Device_43,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos ndhvrd_Device_44,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos ndhvrf_Device_45,,50,5,mtot:dfntrm,nsd:contSD -split_hv_mos phvra_Device_46,,50,5,mtot:dfptrm1,psd:contSD -split_hv_mos phvrb_Device_47,,50,5,mtot:dfptrm1,psd:contSD -split_hv_mos phvrc_Device_48,,50,5,mtot:dfptrm1,psd:contSD -split_hv_mos phvrd_Device_49,,50,5,mtot:dfptrm1,psd:contSD -split_hv_mos phvre_Device_50,,50,5,mtot:dfptrm1,psd:contSD -split_hv_mos phvrf_Device_51,,50,5,mtot:dfptrm1,psd:contSD /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC Successfully created RCX script '/ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/rcx.sh' WARNING (LBRCXM-617): Unable to obtain 1 license(s) for Virtuoso_QRC_Extraction_L 17.10 INFO (LBRCXM-581): Checked out '1' license(s) for Virtuoso_QRC_Extraction_XL 17.10 INFO (LBRCXM-608): Executing command /bin/ksh /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/rcx.sh ##======================================================= ##ADD_EXPLICIT_VIAS=N ##ADD_BULK_TERMINAL=N ##AGDS_FILE=/dev/null ##AGDS_LAYER_MAP_FILE=/dev/null ##HCCI_DEV_PROP_FILE=/dev/null ##AGDS_SPICE_FILE=/dev/null ##AGDS_TEXT_LAYERS= ##ARRAY_VIAS_SPACING= ##ASSURA_RUN_DIR=/ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC ##ASSURA_RUN_NAME=voltage_limiter_conventional_mn_DRC ##BLACK_BOX_CELLS=/dev/null ##BREAK_WIDTH= ##CAP_COUPLING_FACTOR=1.0 ##CAP_EXTRACT_MODE=coupled ##CAP_GROUND=gnd! ##CAP_MODELS=yes ##DANGLINGR=N ##DENSITY_CHECK_METHOD=P ##DELETE_OUTPUT_FILE=N ##DEVICE_FINGER_DELIMITER='@' ##DF2=Y ##DRACULA_RUN_DIR= ##DRACULA_RUN_NAME= ##ENABLESENSITIVITYEXTRACTION=N ##EXCLUDE_FLOAT_LIMIT= ##EXCLUDE_FLOAT_DECOPULING_FACTOR= ##EXCLUDE_FLOATING_NETS=N ##EXCLUDE_NETS_REDUCERC=/dev/null ##EXCLUDE_SELF_CAPS=Y ##IGNORE_GATE_DIFFUSION_FRINGING_CAP=Y ##EXTRACT=both ##EXTRACT_MOS_DIFFUSION_AP=N ##EXTRACT_MOS_DIFFUSION_HIGH= ##EXTRACT_MOS_DIFFUSION_RES=Y ##FILTER_SIZE=2.0 ##FIXED_NETS_FILE=/dev/null ##FMAX= ##FRACTURE_LENGTH_UNITS=MICRONS ##FREQUENCY_FILE=/dev/null ##GROUND_NETS= ##GROUND_NETS_FILE=/dev/null ##GROUND_SUBSTRATE_FLOATING_NETS=N ##HCCI_DEV_PROP=7 ##HCCI_INST_PROP=6 ##HCCI_NET_PROP=5 ##HCCI_RULE_FILE= ##HCCI_RUN_DIR= ##HCCI_RUN_NAME= ##HEADER_FILE=/dev/null ##HIERARCHY_DELIMITER='/' ##OUTPUT_HIERARCHY_DELIMITER='/' ##HRCX_CELLS_FILE=/dev/null ##IMPORT_GLOBALS=Y ##LADDER_NETWORK=N ##LVS_SOURCE=assura ##M_FACTORR= ##M_FACTORW=N ##MACRO_CELL=Y ##MAX_FRACTURE_LENGTH=infinite ##MAX_SIGNALS= ##MERGE_PARALLEL_R=N ##MERGE_PARALLEL_VIA=N ##MINC=1e-17 ##MINC_BY_PERCENTAGE=0.1 ##MINR=0.001 ##NET_NAME_SPACE=layout ##NETS_FILE=/dev/null ##OUTPUT=/ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/extview.tmp ##OUTPUT_NET_NAME_SPACE=layout ##PARASITIC_BLOCKING_DEVICE_CELLS_TYPE=gray ##PARASITIC_CAP_MODELS=no ##PARASITIC_RES_MODELS=no ##PARASITIC_RES_LENGTH=N ##PARASITIC_RES_WIDTH=N ##PARASITIC_RES_WIDTH_DRAWN=N ##PARASITIC_RES_UNIT=N ##PARTIAL_CAP_BLOCKING=N ##PEEC=N ##PIN_ORDER_FILE=/dev/null ##PIPE_ADVGEN= ##PIPE_SPICE2DB= ##POWER_NETS= ##POWER_NETS_FILE=/dev/null ##RC_FREQUENCY= ##RCXDIR=/ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC ##RCXFS_HIGH=N ##RCXFS_NETS_FILE=/dev/null ##RCXFS_TYPE=none ##RCXFS_CUTOFF_DISTANCE= ##RCXFS_CUTOFF_DISTANCE= ##RCXFS_CUTOFF_DISTANCE= ##RCXFS_CUTOFF_DISTANCE= ##RCXFS_CUTOFF_DISTANCE= ##RCXFS_VIA_OFF=N ##REDUCERC=N ##REGION_LIMIT= ##RES_MODELS=yes ##RISE_TIME= ##SAVE_FILL_SHAPES=N ##SINGLE_CAP_EDSPF=N ##SHOW_DIODES=N ##SKIN_FREQUENCY= ##SPEF=N ##SPEF_UNITS= ##SPLIT_PINS=N ##FORCE_SUBCELL_PIN_ORDERS=N ##SPLIT_PINS_DISTANCE= ##SUB_NODE_CHAR='#' ##SUBSTRATE_PROFILE=/dev/null ##SUBSTRATE_STAMPING_OFF=N ##TEMPDIR=/ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/rcx_temp ##TEMPERATURE=27.0 ##TYPE=full ##USER_REGION=/dev/null ##VARIANT_CELL_FILE=/dev/null ##VIA_EFFECT_OFF=N ##VIRTUAL_FILL= ##XREF=/dev/null,/dev/null ##XY_COORDINATES=c,r ##======================================================= CASE_SENSITIVE=TRUE export CASE_SENSITIVE QRC_MOS_LW_PRECISION=y export QRC_MOS_LW_PRECISION TEMPDIR=`setTempDir /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/rcx_temp` setTempDir /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC/rcx_temp export TEMPDIR DEVICE_FINGER_DELIMITER='@' HIERARCHY_DELIMITER='/' OUTPUT_HIERARCHY_DELIMITER='/' cd /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC cat caps2dversion * caps2d version: 10 ENDCAT cat flattransUnit.info meters ENDCAT QRC=Y export QRC cat topcellxcn.info /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC.xcn ENDCAT #==========================================================# # Generate RCX input data from Assura LVS database #==========================================================# GOALIE2DIR=/ECEnet/Apps1/linux/cad12/tools/cadence/EXT171/tools.lnx86/extraction/bin export GOALIE2DIR vdbToRcx /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC \ voltage_limiter_conventional_mn_DRC -unit meters -- -V1 -H satfile -r \ /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC/voltage_limiter_conventional_mn_DRC.xcn \ -df2 -xgl @(#)$CDS: vdbToRcx_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12 01/31/2018 23:40 (sjfnl846) $ 16.1.1 Linux 64 bit - (Fri Mar 17 16:46:12 PDT 2017) Opening LVS data for voltage_limiter_conventional_mn_DRC in /ECEnet/home/student/mehdina94rm/XFAB_XT018/AssuraDRC Open time is 0.0 sec. Build pins/attributes took 0.0 sec. Processing met1_text 0 shapes 0.0 sec. create satfile took 0.02 user, 0.03 sys, 0.00 elapsed, 125912.0 kbytes write edge met1_text took 0.00 user, 0.00 sys, 0.00 elapsed, 126136.0 kbytes Building net map file. 0.0 sec. create netmap file took 0.00 user, 0.00 sys, 0.00 elapsed, 126156.0 kbytes create net file took 0.00 user, 0.00 sys, 0.00 elapsed, 126200.0 kbytes WARNING (LBCLV-5652): No mosfet models provided. Can't create transfile WARNING (LBCLV-5663): No bipolar models provided. Can't create bipolar files WARNING (LBCLV-5660): No resistor models provided. Can't create resistor files WARNING (LBCLV-5654): No capacitor models provided. Can't create capacitor file WARNING (LBCLV-5657): No diode models provided. Can't create diode files WARNING (LBCLV-5706): no generic models in rule file Device creation took 0.0 sec Processing contP 0 shapes 0.0 sec. write edge contP took 0.01 user, 0.00 sys, 0.00 elapsed, 126240.0 kbytes Processing pfox_conn 0 shapes 0.0 sec. write edge pfox_conn took 0.00 user, 0.00 sys, 0.00 elapsed, 126468.0 kbytes Processing gate_T?18587 37 shapes 0.0 sec. write edge gate_T?18587 took 0.00 user, 0.00 sys, 0.00 elapsed, 126624.0 kbytes Processing gate_T?18582 0 shapes 0.0 sec. write edge gate_T?18582 took 0.00 user, 0.00 sys, 0.00 elapsed, 126828.0 kbytes Processing gate_T?18576 0 shapes 0.0 sec. write edge gate_T?18576 took 0.00 user, 0.01 sys, 0.00 elapsed, 126964.0 kbytes Processing gate_T?18570 0 shapes 0.0 sec. write edge gate_T?18570 took 0.00 user, 0.00 sys, 0.00 elapsed, 127100.0 kbytes Processing via2_conn 0 shapes 0.0 sec. write edge via2_conn took 0.00 user, 0.00 sys, 0.00 elapsed, 127236.0 kbytes Processing gate_T?18564 0 shapes 0.0 sec. write edge gate_T?18564 took 0.00 user, 0.00 sys, 0.00 elapsed, 127372.0 kbytes Processing via1_conn 0 shapes 0.0 sec. write edge via1_conn took 0.00 user, 0.00 sys, 0.00 elapsed, 127508.0 kbytes Processing gate_T?18558 0 shapes 0.0 sec. write edge gate_T?18558 took 0.00 user, 0.00 sys, 0.00 elapsed, 127644.0 kbytes Processing cont_conn 0 shapes 0.0 sec. write edge cont_conn took 0.00 user, 0.00 sys, 0.00 elapsed, 127780.0 kbytes Processing sd 51 shapes 0.0 sec. write edge sd took 0.00 user, 0.00 sys, 0.00 elapsed, 127924.0 kbytes Processing pfox 0 shapes 0.0 sec. write edge pfox took 0.00 user, 0.00 sys, 0.00 elapsed, 128148.0 kbytes Processing met3trm_dg 0 shapes 0.0 sec. write edge met3trm_dg took 0.00 user, 0.00 sys, 0.00 elapsed, 128300.0 kbytes Processing met2trm_dg 0 shapes 0.0 sec. write edge met2trm_dg took 0.00 user, 0.00 sys, 0.00 elapsed, 128456.0 kbytes Processing met1trm_dg 0 shapes 0.0 sec. write edge met1trm_dg took 0.00 user, 0.00 sys, 0.00 elapsed, 128608.0 kbytes Processing polytrm_dg 0 shapes 0.0 sec. write edge polytrm_dg took 0.00 user, 0.00 sys, 0.00 elapsed, 128760.0 kbytes Processing via1 438 shapes 0.0 sec. write edge via1 took 0.01 user, 0.00 sys, 0.00 elapsed, 128912.0 kbytes Processing ptapc 0 shapes 0.0 sec. write edge ptapc took 0.00 user, 0.00 sys, 0.00 elapsed, 129064.0 kbytes Processing ntapc 0 shapes 0.0 sec. write edge ntapc took 0.00 user, 0.01 sys, 0.00 elapsed, 129216.0 kbytes Processing psd 0 shapes 0.0 sec. write edge psd took 0.00 user, 0.00 sys, 0.00 elapsed, 129368.0 kbytes Processing nsd 0 shapes 0.0 sec. write edge nsd took 0.00 user, 0.00 sys, 0.00 elapsed, 129520.0 kbytes Processing contSD 0 shapes 0.0 sec. write edge contSD took 0.00 user, 0.00 sys, 0.00 elapsed, 129672.0 kbytes Processing bulk 0 shapes 0.0 sec. write edge bulk took 0.00 user, 0.00 sys, 0.00 elapsed, 129808.0 kbytes Processing via2CON 254 shapes 0.0 sec. write edge via2CON took 0.00 user, 0.00 sys, 0.00 elapsed, 129960.0 kbytes Processing met3trm 0 shapes 0.0 sec. write edge met3trm took 0.00 user, 0.00 sys, 0.00 elapsed, 130104.0 kbytes Processing met2trm 0 shapes 0.0 sec. write edge met2trm took 0.00 user, 0.00 sys, 1.00 elapsed, 130256.0 kbytes Processing met1trm 0 shapes 0.0 sec. write edge met1trm took 0.00 user, 0.00 sys, 0.00 elapsed, 130408.0 kbytes Processing nwtrm1 0 shapes 0.0 sec. write edge nwtrm1 took 0.00 user, 0.00 sys, 0.00 elapsed, 130560.0 kbytes Processing nwtrm 0 shapes 0.0 sec. write edge nwtrm took 0.00 user, 0.00 sys, 0.00 elapsed, 130696.0 kbytes Processing polytrm 0 shapes 0.0 sec. write edge polytrm took 0.00 user, 0.00 sys, 0.00 elapsed, 130832.0 kbytes Processing pdiff 0 shapes 0.0 sec. write edge pdiff took 0.00 user, 0.01 sys, 0.00 elapsed, 130984.0 kbytes Processing ndiff 0 shapes 0.0 sec. write edge ndiff took 0.00 user, 0.00 sys, 0.00 elapsed, 131136.0 kbytes Processing cont 887 shapes 0.0 sec. write edge cont took 0.01 user, 0.00 sys, 0.00 elapsed, 131288.0 kbytes Processing met3 9 shapes 0.0 sec. write edge met3 took 0.00 user, 0.00 sys, 0.00 elapsed, 131448.0 kbytes Processing met2 34 shapes 0.0 sec. write edge met2 took 0.00 user, 0.00 sys, 0.00 elapsed, 131608.0 kbytes Processing met1 56 shapes 0.0 sec. write edge met1 took 0.00 user, 0.00 sys, 0.00 elapsed, 131764.0 kbytes Processing poly 10 shapes 0.0 sec. write edge poly took 0.00 user, 0.00 sys, 0.00 elapsed, 131920.0 kbytes sort edges took 0.13 user, 0.62 sys, 1.00 elapsed, 2072.0 kbytes sort edges and labels took 0.25 user, 0.79 sys, 1.00 elapsed, 132076.0 kbytes vdbToRcx System Usage: Elapsed: 2 seconds. CPU: 0.1 seconds Memory 13 Meg GOALIE2DIR=/ECEnet/Apps1/linux/cad12/tools/cadence/EXT171/tools.lnx86/extraction/bin/64bit/ export GOALIE2DIR #==========================================================# # Generate power list #==========================================================# cat global.net > power_list #==========================================================# # Create ports for abutment #==========================================================# geom -C nsd - nsd,1,i,1 geom -C ptapc - ptapc,1,i,1 inter nsd ptapc -t nsd_ptapc_butt:edge geom -C psd - psd,1,i,1 inter psd ptapc -t psd_ptapc_butt:edge geom -C ndiff - ndiff,1,i,1 inter ndiff ptapc -t ndiff_ptapc_butt:edge geom -C ntapc - ntapc,1,i,1 inter psd ntapc -t psd_ntapc_butt:edge inter nsd ntapc -t nsd_ntapc_butt:edge geom -C pdiff - pdiff,1,i,1 inter pdiff ntapc -t pdiff_ntapc_butt:edge /bin/mv -f nwtrm nwtrm_orig epick nwtrm_orig nwtrm /bin/mv -f bulk bulk_orig epick bulk_orig bulk /bin/mv -f pfox pfox_orig epick pfox_orig pfox /bin/mv -f poly poly_orig epick poly_orig poly /bin/mv -f gate_T?18558 gate_T?18558_orig epick gate_T?18558_orig gate_T?18558 /bin/mv -f met1 met1_orig epick met1_orig met1 /bin/mv -f sd sd_orig epick sd_orig sd /bin/mv -f gate_T?18564 gate_T?18564_orig epick gate_T?18564_orig gate_T?18564 /bin/mv -f met2 met2_orig epick met2_orig met2 /bin/mv -f gate_T?18570 gate_T?18570_orig epick gate_T?18570_orig gate_T?18570 /bin/mv -f met3 met3_orig epick met3_orig met3 /bin/mv -f gate_T?18576 gate_T?18576_orig epick gate_T?18576_orig gate_T?18576 /bin/mv -f gate_T?18582 gate_T?18582_orig epick gate_T?18582_orig gate_T?18582 /bin/mv -f gate_T?18587 gate_T?18587_orig epick gate_T?18587_orig gate_T?18587 #==========================================================# # Ensure vias do not extend beyond routing #==========================================================# geom -V nsd ptapc - nsd_ptapc_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V nsd nsd_ptapc_butt - nsd_nsd_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V ptapc nsd_ptapc_butt - ptapc_nsd_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V psd ptapc - psd_ptapc_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V psd psd_ptapc_butt - psd_psd_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V ptapc psd_ptapc_butt - ptapc_psd_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V ndiff ptapc - ndiff_ptapc_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2116.0 kbytes geom -V ndiff ndiff_ptapc_butt - ndiff_ndiff_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V ptapc ndiff_ptapc_butt - ptapc_ndiff_ptapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V psd ntapc - psd_ntapc_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V psd psd_ntapc_butt - psd_psd_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V ntapc psd_ntapc_butt - ntapc_psd_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V nsd ntapc - nsd_ntapc_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V nsd nsd_ntapc_butt - nsd_nsd_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V ntapc nsd_ntapc_butt - ntapc_nsd_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V pdiff ntapc - pdiff_ntapc_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V pdiff pdiff_ntapc_butt - pdiff_pdiff_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 1.00 elapsed, 2120.0 kbytes geom -V ntapc pdiff_ntapc_butt - ntapc_pdiff_ntapc_butt_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V cont met1trm ndiff - cont_met1trm_ndiff,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V cont met1trm pdiff - cont_met1trm_pdiff,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V cont ndiff pdiff - cont_ndiff_pdiff,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD met1trm nsd - contSD_met1trm_nsd,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V contSD met1trm psd - contSD_met1trm_psd,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD met1trm ntapc - contSD_met1trm_ntapc,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD met1trm ptapc - contSD_met1trm_ptapc,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V contSD nsd psd - contSD_nsd_psd,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD nsd ntapc - contSD_nsd_ntapc,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V contSD nsd ptapc - contSD_nsd_ptapc,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD psd ntapc - contSD_psd_ntapc,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V contSD psd ptapc - contSD_psd_ptapc,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V contSD ntapc ptapc - contSD_ntapc_ptapc,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V contP met1trm polytrm - contP,111,i,2 geom took 0.00 user, 0.01 sys, 1.00 elapsed, 2116.0 kbytes geom -V via1 met1trm met2trm - via1_met1trm_met2trm,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V via2CON met2trm met3trm - via2CON_met2trm_met3trm,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V nwtrm ntapc - nwtrm_ntapc_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2116.0 kbytes geom -V nwtrm1 ntapc - nwtrm1_ntapc_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V bulk ptapc - bulk_ptapc_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V polytrm_dg polytrm - polytrm_dg_polytrm_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V met1trm_dg met1trm - met1trm_dg_met1trm_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V met2trm_dg met2trm - met2trm_dg_met2trm_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V met3trm_dg met3trm - met3trm_dg_met3trm_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V pfox_conn pfox poly - pfox_conn,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V cont_conn cont poly - cont_conn,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V gate_T?18558 poly - gate_T?18558_poly_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V cont met1 poly - cont_met1_poly,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2120.0 kbytes geom -V cont met1 sd - cont_met1_sd,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V cont poly sd - cont_poly_sd,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V via1_conn via1 met1 - via1_conn,111,i,2 geom took 0.00 user, 0.01 sys, 0.00 elapsed, 2124.0 kbytes geom -V gate_T?18564 poly - gate_T?18564_poly_ovia,11,i,1 geom took 0.00 user, 0.01 sys, 1.00 elapsed, 2120.0 kbytes geom -V via1 met2 met1 - via1_met2_met1,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2124.0 kbytes geom -V via2_conn via2CON met2 - via2_conn,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V gate_T?18570 poly - gate_T?18570_poly_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V via2CON met3 met2 - via2CON_met3_met2,111,i,2 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V gate_T?18576 poly - gate_T?18576_poly_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V gate_T?18582 poly - gate_T?18582_poly_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes geom -V gate_T?18587 poly - gate_T?18587_poly_ovia,11,i,1 geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2120.0 kbytes /bin/mv -f nwtrm_orig nwtrm /bin/mv -f bulk_orig bulk /bin/mv -f pfox_orig pfox /bin/mv -f poly_orig poly /bin/mv -f gate_T?18558_orig gate_T?18558 /bin/mv -f met1_orig met1 /bin/mv -f sd_orig sd /bin/mv -f gate_T?18564_orig gate_T?18564 /bin/mv -f met2_orig met2 /bin/mv -f gate_T?18570_orig gate_T?18570 /bin/mv -f met3_orig met3 /bin/mv -f gate_T?18576_orig gate_T?18576 /bin/mv -f gate_T?18582_orig gate_T?18582 /bin/mv -f gate_T?18587_orig gate_T?18587 #==========================================================# # Flatten net file, routing, via and device layers #==========================================================# SAVEDIR=`beginFlattenInputs` beginFlattenInputs export SAVEDIR /bin/mv -f NET h_NET flatnet -V -li -h '/' h_NET NET netprint -V -N1 power_list:power_list_nums NET flattenLayers -m cont contSD via1 via2CON met3trm met2trm met1trm polytrm nsd \ psd nwtrm bulk nsd_ptapc_ovia ptapc nsd_nsd_ptapc_butt_ovia \ nsd_ptapc_butt ptapc_nsd_ptapc_butt_ovia psd_ptapc_ovia \ psd_psd_ptapc_butt_ovia psd_ptapc_butt ptapc_psd_ptapc_butt_ovia \ ndiff_ptapc_ovia ndiff ndiff_ndiff_ptapc_butt_ovia ndiff_ptapc_butt \ ptapc_ndiff_ptapc_butt_ovia psd_ntapc_ovia ntapc \ psd_psd_ntapc_butt_ovia psd_ntapc_butt ntapc_psd_ntapc_butt_ovia \ nsd_ntapc_ovia nsd_nsd_ntapc_butt_ovia nsd_ntapc_butt \ ntapc_nsd_ntapc_butt_ovia pdiff_ntapc_ovia pdiff \ pdiff_pdiff_ntapc_butt_ovia pdiff_ntapc_butt \ ntapc_pdiff_ntapc_butt_ovia cont_met1trm_ndiff cont_met1trm_pdiff \ cont_ndiff_pdiff contSD_met1trm_nsd contSD_met1trm_psd \ contSD_met1trm_ntapc contSD_met1trm_ptapc contSD_nsd_psd \ contSD_nsd_ntapc contSD_nsd_ptapc contSD_psd_ntapc contSD_psd_ptapc \ contSD_ntapc_ptapc contP via1_met1trm_met2trm via2CON_met2trm_met3trm \ nwtrm_ntapc_ovia nwtrm1_ntapc_ovia nwtrm1 bulk_ptapc_ovia \ polytrm_dg_polytrm_ovia polytrm_dg met1trm_dg_met1trm_ovia met1trm_dg \ met2trm_dg_met2trm_ovia met2trm_dg met3trm_dg_met3trm_ovia met3trm_dg \ pfox_conn pfox poly cont_conn gate_T?18558_poly_ovia gate_T?18558 \ cont_met1_poly met1 cont_met1_sd sd cont_poly_sd via1_conn \ gate_T?18564_poly_ovia gate_T?18564 via1_met2_met1 met2 via2_conn \ gate_T?18570_poly_ovia gate_T?18570 via2CON_met3_met2 met3 \ gate_T?18576_poly_ovia gate_T?18576 gate_T?18582_poly_ovia \ gate_T?18582 gate_T?18587_poly_ovia gate_T?18587 flattub took 0.12 user, 0.31 sys, 2.00 elapsed, 3704.0 kbytes endFlattenInputs #==========================================================# # Initialize CAP_GROUND variable #==========================================================# CAP_GROUND=`findCapGround -g gnd! NET` findCapGround -g gnd! NET ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found. Check if net 'gnd!' exists in design and has the correct ?netNameSpace (schematic, layout) specified in RSF. If the ground signal name cannot be identified, use 'capgen -cap_ground_layer' option. ERROR (LBRCXM-609): Bad return status from RCX run. 0xff00 INFO (LBRCXM-709): ***** Quantus QRC terminated abnormally ***** I have tried different versions of the Cadence from 6.1.5 up to 6.1.8. I have also contacted the Cadence support but they told that I am not an authorized person to contact them and I should contact the student support but they are responsive. University also is not responsive. Do you have any other suggestion that I can consider?

Yes, case submitted, latest ISR for 17.2 installed, Windows 10. I have never seen it either and I've been on their tools since 1980 (hence my handle)

Look like it removes the entire symbol. Would that be possible to remove part of the silkscreen of a particular symbol?

Element: Line (only!). You obviously have the 'symbol' selected in you Find Filter. Turn all off except Line or Line Segment and delete.

Holy... that's huge! What happens if you start Allegro in save mode? (to exclude any use setting)

Newbie question here : I get way too much warnings about "Possible pin type conflict GND". Many tied to IC GND power Type pin. In the ERC Matrix, Power to Power shouldn't report any warnings...