Hi Max, there is my code: tf=techOpenTechFile(“techLibname” “tech.db” “a”) myVia=techCreateStdViaDef(tf “M2_M1a” “Met1” “Met2” list(“Via1” 0.19 0.19) list(1 1 ‘(0.22 0.22)) ‘(0.05 0.05) ‘(0.05 0.05) ‘(0.0 0.0) ‘(0.0 0.0) ‘(0.0 0.0) These codes are in a script and the CIW return “t” when I load the script.After more detailed check,I find that I can find the new via’s definition from the tech file that I dump from my tech library after I load the script. However,My orignial tech file still has no the via’s definition and I cannot still add the new via to my cell because I can not see the new via in “Create Via” form. Besides,let me tell you how I define a new via manually.I added a new via’s definition to my tech file’ s standardViaDefs section and then added the new via’s definition name to all the interconnect section and it works. Regards John![]()
↧
RE: How to define a new standard via
↧
RE: Cadence Virtuoso/Design Framework Compatibility with MATLAB
[quote userid="374799" url="~/cadence_technology_forums/f/mixed-signal-design/40926/cadence-virtuoso-design-framework-compatibility-with-matlab/1358456#1358456"][/quote] By MMSIM stream, do you mean Spectre Virtuoso/Cadence version IC5.x or IC6.1.6 and previous ? By ADE Explorer and Assember, do you mean Spectre Virtuoso/Cadence version IC6.1.7 and above ? By MMSIM, I mean the release that spectre is delivered within. This has not been part of the IC stream since 2004, and there were releases such as MMSIM60, MMSIM61 ... MMSIM151 (one a year roughly since 2004). In 2016 though, we renamed the release stream to be called SPECTRE161 and since then we've had SPECTRE171 and SPECTRE181. The cds_srr interface is shipped and supported via the MMSIM/SPECTRE installation (although it is actually present in the IC617 release and later, mainly for use by the new ADE integration). By ADE Explorer and Assembler, I'm talking about the new generation of ADE tools, as opposed to ADE L and ADE XL (and GXL). These were introduced in IC617, but ADE L and XL still exist in IC617 too - you have to consciously use the new tools (the storage is different). There is plenty of information on the Cadence public site and support site on adopting ADE Explorer and Assembler, including a rapid adoption kit (a workshop to show you how to migrate to the new tools). Regards, Andrew.![]()
↧
↧
RE: How to define a new standard via
Hi John, In addition to adding the stdVia def, you need to add it into the validVias interconnect constraint in the constraint group being used for Vias. That's what you've been doing manually, but if adding via SKILL you'd need to do it then too. The constraint group used is the one on Options->Editor for via. You can do it this way: cv=geGetEditCellView() cgName=cstGetDefaultConstraintGroupName(cv "Via") ; this should be what is on the Options->Editor cg=cstFindConstraintGroupIn(tf cgName) vv=cstFindFirstConstraint(cg "validVias") vv~>value=cons("M2_M1a" vv~>value) Regards, Andrew.![]()
↧
RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
Hello Andrew, This is the return for "virtuoso -W". sub-version IC6.1.6-64b.500.4 Regards , Rena![]()
↧
facing sync issue while generating the netlist
I am using Allegro design entry HDL 17.2. i updated in Schematic only a specific component without any changes in the existing board(.cpm file) .while generating a netlist i am facing Synchronization issue. If i am using the old board without any change also having the same issue.![]()
↧
↧
RE: expression problem from ac sweep
Hello Shawn and Andrew, thank you very much , i got a good varactor exactly as you described in you test bench methodics.![]()
↧
SiFive: The Magnificent Seven
At least for now, I think that the most significant of the RISC-V processor companies is SiFive. There are two reasons for this: they started first, and they are an IP licensing company (as well as a chip company), not someone creating an implementation solely for their internal use. This could change since Western Digital is open-sourcing its core, several other processor vendors are switching from proprietary ISAs to RISC-V (such as Codassip, Andes, Cortus...), and Esperanto is designing a higher performance out-of-order core that you will be able to license. For more background on some of these, see my post from last week, RISC-V Cores: SweRV and ET-Maxion . SiFive Started First SiFive started ahead of everyone else since they are basically the group that both developed the RISC-V instruction set architecture (ISA) and created the first implementation (the Rocket core). I first came across RISC-V back in May 2016 at EDPS when they presented Chisel, the design language that Berkeley created so that they could build chips with a few semiconductor experts and an army of computer science undergraduates. Given that the DP in EDPS stands for "design process", the focus was more on how it was designed, with the RISC-V ISA and the core almost mentioned in passing. You can read about that in my post A Raven Has Landed: RISC-V and Chisel . A lot more people came across RISC-V later that year when Krste Asańovic presented to a standing-room-only crowd at the DAC pavilion. You can read about that in my post RISC-V—Instruction Sets Want to Be Free . That was where, with classic British understatement (he studied in the UK), he said: Our modest goal is to become the industry standard for all computing devices. Well, there is a long way to go. But I think it is already true to say that they are the academic standard for all courses on computer architecture. Of course, it helps a lot that Dave Patterson is also one of the people who have contributed to RISC-V, and along with John Hennessy, he literally writes the books on computer architecture—at least the standard ones used for both undergraduate- and masters-level teaching. When SiFive started, they had the brains trust of the RISC-V ISA, they had the Berkeley cores, and they knew Chisel already. I first wrote about them in September 2016, in the first year I heard about RISC-V, in my post SiFive: a RISC-V Fabless Semiconductor Company . With those advantages, they delivered their first silicon before the end of 2016, the FE310 SoC (see my post RISC-V Available in Silicon for details). They went on to produce a series of cores and now their portfolio contains series called E2, E3, S5, and U5. At the Linley Conference on Halloween last year, they announced the 7 series: the E7 series, the S7 series, and the U7 series. See below for more details. They gave a little more detail at the recent RISC-V Summit too, eating their own dogfood by presenting their slides on a board based on one of their own RISC-V processors. There has been huge interest. Over 500 fabless semiconductor companies have contacted SiFive. There was a global city tour with 22 stops, and over 5,000 people registered. A video they sponsored was viewed over 2.5M times. IP Licensing As a way of scaling an architecture and propagating it to the world, nothing beats IP licensing. I first saw this with Arm. The first Arm processor was designed in-house at Acorn in 1985 to power their own next-generation PC. The A in Arm originally stood for Acorn, not Advanced. Arm was spun out of Acorn as a standalone company when Apple wanted to use it for the Newton. VLSI Technology, where I worked at the time, was the semiconductor supplier. We all expected that the Newton would be a huge success (the CEO of Apple at the time, John Sculley, was talking about billions of devices...which kinda came true if you think of the iPhone as a direct descendent, and it is powered by Arm). In that era, a microprocessor like Arm would have a primary source (VLSI in the case of Arm), and often a second source so that customers weren't dependent on a single supplier or perhaps even a single fab. For example, VLSI was a second source for Hitachi's H8 microprocessor. More famously, AMD was a second source for Intel's x86 chips, which is how they came to even compete in that market (it wais a long complicated battle involving lots of lawyers). If the Newton had been the success originally envisioned, presumably at some point Apple would have insisted on a second source, that was how the world worked. But the world stopped working like that. Many semiconductor companies had their own microprocessor, not just Hitachi and Intel. The Zilog Z8, Motorola had several, TI. IBM, Motorola (pre-Freescale), and Apple created the PowerPC for the Mac, with the idea that IBM and Freescale would supply Apple. This was all at the end of the era when a processor would occupy a whole chip. The next era would be when a processor would occupy some of a chip to provide programmability, and specialized logic would fill the rest of the die. The processors became known as embedded processors, and that type of chip became known as a system-on-chip or SoC. This caused a big problem for all the semiconductor manufacturers who didn't already have their own in-house 32-bit microprocessor, since they would not be able to participate in building SoCs, and eventually would either be forced out of the semiconductor market completely, or end up as niche suppliers (often very profitable ones: for many years Linear Technology had the highest profit margins of any semiconductor company supplying only analog chips). These companies need to license a processor. Since the Newton was clearly not taking off like a rocketship, Arm started licensing their processors to anyone, and they were in the right place at the right time. The other company in the processor IP business was MIPS. Arm found their rocketship when Nokia decided to use Arm for their cellphones, if they could fix the code-density problem. Nokia, Arm, and TI agreed on the Thumb extension, and since that day pretty much every cellphone from any manufacturer contained an Arm (for years, the ARM7TDMI). MIPS held a strong position in set-top-boxes and routers, but they never achieved anything like the volume of cellphones. Arm, of course, got acqured by Softbank. MIPS took a (very) circuitous route and is now owned by Wave Computing who are open-sourcing the cores. SiFive is a semiconductor company, in the sense that they will do a custom chip for you, manufacture it, and then sell you finished products, just like any other fabless semiconductor company. But they also license all their cores as IP, and many (all?) of them are also open-sourced. Also, like Lay's potato chips, bet you can't just eat one. Or in their case, produce just one core family. The 7 Series The 7-series that SiFive announced at Linley consists of: the E7 series, 32-bit embedded processors the S7 series, 64-bit embedded processors the U7 series, 64-bit application processors Compared to the equivalent cores in the previous 5-series, these cores have a 60% increase in CoreMarks/MHz, a 40% increase in DMIPS/MHz, and a 10% increase in Fmax (in the same process). The E7 is dual-issue, in-order, 8-stage Harvard pipeline, with optional instruction and data caches, and is multi-core capable (with other options too). 2.3 DMIPS/MHz, 4.9 CoreKarks/MHz. The S7 series has a similar pipeline except that it is 64-bit. 2.5 DMIPS/MHz, 4.9 CoreMarks/MHz. The U7 series is also 64-bit but with Sv39 virtual memory support, supports heterogeneous multi-core clustering (with S7 and U7 cores mixed), and various functional safety and security features (such as being able to disable dynamic branch prediction for deterministic execution). 2.5 DMIPS/MHz, 4.9 CoreMarks/Mhz. All three cores have basically the same pipeline, shown below: FADU Another interesting presentation during the RISC-V summit was by FADU's CEO Jihyo Lee about their Annapurna SSD controller (note: this has nothing to do with Annapurna Labs or the recent announcements from AWS). FADU was founded on the basis that people need radically new solutions and not everything can come from simply writing software, and incrementally improving the hardware. The latest SSD controllers use more modern interfaces and so deliver five times the throughput, but unfortunately, they require five times the power to do so. The target market is the datacenter, and one of the biggest challenges in datacenters is power: both getting electricity in and getting heat out. The overall performance of their controller is impressive, with 3.5GB/s throughput and 800K IOPS at less than 1.8W. It goes in the FADU Bravo Series Enterprise SSD, and is the world's first RISC-V SSD controller (I am assuming Western Digital won't be far behind). Under the hood, it uses three SiFive E51 cores. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧
tran statement in spectre
I have used the below commands for tran statement for 1000 point tran1 tran stop=4e-8 strobeperiod=4e-11 tran1 tran start=0 stop=4e-8 strobeperiod=4e-11 but strange, in all print file i am able to view more than 1150 points. which is not required for my application. can i get a correct trans statement for 1000 points, can be considered the above range. Regards, Manjunath N![]()
↧
Custom report generation
I am trying to create a custom report in Orcad PCB Editor that outputs the internal Part Number we have assigned. My schematic symbol has defined a property of "User Part Number". That creates Attached text: class = USER PART NUMBER subclass = ASSEMBLY_TOP value = 5041210 in the footprint. My question is what do I need to add to the symbol to get the part number to show up in the report using: # This is an extract command file # generated by the Extract UI. # COMPONENT REFDES REFDES_SORT SYM_CENTER_X SYM_CENTER_Y PART_NUMBER END![]()
↧
↧
Viewing task values in Simvision
Hello, I'm working on creating a robust simulation environment for a project and I'm not super familiar with Simvision/Incisive. In modelsim you can view the values inside task calls the same way you view signals in modules. Is there a way to do this in Simvision? I'm thinking maybe it has to do with the $shm_probe command. I'm doing $shm_probe(name, "ACM"). Is this possible with the Cadence tools? Thank you, Dylan![]()
↧
RE: Viewing task values in Simvision
Hi Dylan. In general we recommend not embedding waveform probing in the SV code, as it's less flexible than using the Tcl interface. With Tcl, there is a "probe" command which allows you to specify the hierarchy to send to the waveform file, and at the same time you specify the types of design objects that are included, e.g. just i/o ports, internal nets, assertions etc. This can optionally include tasks and functions as well as memories. For example: "probe -create -shm top.dut -all -depth all -tasks -functions". Full documentation here: https://support.cadence.com/apex/techpubDocViewerPage?xmlName=tclcmdref.xml&title=Xcelium%20Simulator%20Tcl%20Command%20Reference%20--%20probe%20-%202.35.4%20probe%20Command%20Syntax&hash=probe-probecommand:syntaxprobeCommandSyntax&c_version=18.09&path=tclcmdref/tclcmdref18.09/probe.html#probe-probecommand:syntaxprobeCommandSyntax If you really want to stick with $shm_probe, add "T" to the mode string. See https://support.cadence.com/apex/techpubDocViewerPage?xmlName=svsim.xml&title=Debugging%20SystemVerilog%20--%20Accessing%20Design%20Objects%20with%20Tcl%20-%20Probing%20Compilation%20Units%20with%20Tcl%20and%20System%20Tasks&hash=AccessingDesignObjectswithTcl-1057261ProbingCompilationUnitswithTclandSystemTasks&c_version=18.09&path=svsim/svsim18.09/Accessing_Design_Objects_with_Tcl.html#AccessingDesignObjectswithTcl-1057261ProbingCompilationUnitswithTclandSystemTasks for all the options.![]()
↧
RE: Viewing task values in Simvision
Hi Steve, Thanks for the very fast reply. That worked perfectly!![]()
↧
Encryption of Capture tcl script
Hello, I need to encrypt a sensitive Capture tcl script. Page 106 of the Capture tcl/tk Application Note mentions the ''orcad::encrypt" command, however when I try to run from the Capture Command Window I get: [ 1]invalid command name "orcad::encrypt" I am using Capture 17.2-2016. Could you please advise ? Many thanks.![]()
↧
↧
RE: Viewing task values in Simvision
One more quick question. Can an automatic task's waveforms be shown? I have an automatic task but when I drag it into the signal window nothing shows up. If the task is static it works as expected.![]()
↧
Improved ACE/AXI backdoor access
A new application note describes the improved backdoor access to the embedded memory in slave instances of ACE/AXI Verification IP (VIP). You will also find recommendations and how this functionality is supported before and after the backdoor access improvements.![]()
↧
How to access Verification IP documents?
The easiest way to access Cadence Verification IP product documents is using the support site for VIP products. Starting the VIPCAT release 11.30.058, you can also download the document library. Go to download.cadence.com . Click the link, VIPCAT113. Select the doc package and download.![]()
↧
RE: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Well, the credit goes to Andrew for writing the solution. ;) Please remember to mention the performance impact to your designers.![]()
↧
↧
RE: tran statement in spectre
OK, but you didn't say how you are generating this print file. Please read Guidelines for the Custom IC Design Forum as this gives some suggestions as to how to ask a good question - the more precise the question, the more precise the answer or even more likely that you'll even get an answer. I cannot guess... Andrew.![]()
↧
insert option diasbled
Hello, when i try to insert a photo or anything else in the "insert" options" it just turns the screen into gray . i know that its the wrong formus, didnt know where to address with this issue. Thanks![]()
↧
RE: Unable to run an ocean script after receiving the message *WARNING* (infile): not a normal file
This is a bit odd. I've found only a single (rather old) report of this happening with a tmpfs filesystem (and we couldn't reproduce it). As far as I can see, SKILL issues this message if the file is not one of three types (from the fstat man page): regular file character device FIFO Can you check what the UNIX "stat" command reports on this file (the one reported in the warning): /usr/bin/stat /path/to/your/file Regards, Andrew.![]()
↧